Lid Layer Buffer Structure for Thermal Stress in Chip Packages

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In semiconductor packaging, thermal expansion mismatches between chips and substrates cause warpage and stress, leading to potential delamination or crack issues in adhesive layers, which can degrade package performance and reliability.

Innovation Solution

A package structure is designed with a stiffener ring and a lid layer having an opening to break stress caused by thermal expansion mismatches, and an embedded buffer layer in the lid layer to prevent electromagnetic interference and further reduce stress, enhancing the reliability of the package.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If a lid layer is used to cover the chip and substrate, then electromagnetic interference is prevented, but thermal expansion stress causes warpage and delamination

Engineering Contradiction:
Improveelectromagnetic interferenceVSAvoidadhesive layer delamination
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The lid layer is segmented by introducing openings that divide it into multiple regions. This segmentation allows different portions of the lid layer to move independently during thermal expansion, reducing overall stress while maintaining electromagnetic shielding in the solid portions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The lid layer is designed with non-uniform structure through openings, creating local variations in stress distribution. Areas with openings have reduced stress concentration, while areas without openings maintain electromagnetic shielding, achieving local optimization of both stress management and EMI protection.

Inventive Principle:
Principle #3Local quality

2Strength

If the lid layer is made continuous to improve structural strength, then warpage resistance increases, but thermal stress concentration causes crack issues

Engineering Contradiction:
Improvewarpage resistanceVSAvoidthermal stress concentration
Core Design Contradiction:
StrengthVSObject-affected harmful factors

Solution Approach 1:

The continuous lid layer is divided into multiple segments by openings, allowing each segment to expand and contract independently during thermal cycling. This reduces stress concentration at any single location while maintaining overall structural integrity and warpage resistance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The openings act as intermediary spaces that accommodate thermal expansion differences between the chip and substrate. These voids serve as stress relief zones that prevent crack propagation while the surrounding lid material maintains structural strength.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If adhesive layers are used to bond components, then assembly is simplified, but thermal expansion mismatches cause delamination

Engineering Contradiction:
Improveassembly simplicityVSAvoidadhesive layer bonding
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The openings in the lid layer serve as pre-designed stress relief structures that cushion against thermal expansion forces before they can transmit to the adhesive layers. This beforehand cushioning prevents delamination while maintaining simple adhesive bonding processes.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

Material is extracted from the lid layer to create openings, removing the source of stress concentration that would otherwise transfer to the adhesive layers. This extraction reduces thermal stress transmission to the bonds while maintaining assembly simplicity.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces thermally-induced stress, preventing delamination and crack issues in the adhesive layers, thereby improving the reliability and performance of the semiconductor package by managing thermal expansion mismatches and electromagnetic interference.

Implementation Method 1

thermal expansion mismatches between chips and substrates cause warpage and stress

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Implementation Method 2

A package structure is designed with a stiffener ring and a lid layer having an opening to break stress caused by thermal expansion mismatches

Methodology Applied
Scientific EffectStress relaxation: Stress Relaxation

Implementation Method 3

an embedded buffer layer in the lid layer to prevent electromagnetic interference

Methodology Applied
Scientific EffectElectromagnetic shielding: Faraday Cage

Data Source

PatentUS12009278B2Package structure with buffer layer embedded in lid layer
Publication Date: 2024.06.11 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12009278B2 patent drawing
  • US12009278B2 patent drawing
  • US12009278B2 patent drawing

AI summary

Provided is a package structure including a substrate, a stiffener ring, an eccentric die, a lid layer, and a buffer layer. The stiffener ring is disposed on the substrate. The stiffener ring has an inner perimeter to enclose an accommodation area. The eccentric die is disposed within the accommodation area on the substrate. The eccentric die is offset from a center of the accommodation area to close to a first side of the stiffener ring. The lid layer is disposed on the stiffener ring and overlays the eccentric die. The buffer layer is embedded in the lid layer between the first side of the stiffener ring and the eccentric die. The buffer layer has a thickness less than a thickness of the lid layer.