LiDAR Point Cloud ISP Buffer Sharing to Cut Delay and Chip Area

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Solution Overview

Problem

Existing image signal processors (ISPs) in LiDAR chips face high overall delay and increased power consumption due to their serial data stream processing structure, where each algorithm level requires dedicated buffer spaces, leading to increased chip area and power consumption.

Innovation Solution

Implement a parallel data stream processing structure where the first-, second-, and third-level algorithms share a buffer space, allowing simultaneous input of partially processed data based on delay differences between the second- and third-level algorithms, reducing the need for individual buffer spaces and minimizing overall delay.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a serial data stream processing structure is used where each algorithm level has dedicated buffer space, then data processing can be performed sequentially through each level, but the chip area increases and power consumption increases

Engineering Contradiction:
Improvedata processing capabilityVSAvoidchip area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent merges the buffer spaces of multiple algorithm levels into a shared buffer space. Instead of having separate buffer spaces for each algorithm level (first-level, second-level, third-level algorithms), a single shared buffer space is used to store intermediate data for all levels, thereby reducing the total chip area while maintaining the serial processing capability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shared buffer space serves multiple functions and multiple algorithm levels simultaneously. It acts as the buffer for the first-level algorithm, the second-level algorithm, and the third-level algorithm, making a single component universal for data storage across different processing stages, thus reducing redundancy in chip area.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If a serial data stream processing structure is used where each algorithm level has dedicated buffer space, then data processing can be performed sequentially through each level, but power consumption increases

Engineering Contradiction:
Improvedata processing capabilityVSAvoidchip power consumption
Core Design Contradiction:
ProductivityVSUse of energy by stationary object

Solution Approach 1:

By merging multiple dedicated buffer spaces into a single shared buffer space, the patent reduces the total number of buffer components. This reduction in component count directly lowers the power consumption of the chip, as fewer memory elements are actively managing data storage across algorithm levels.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The universal shared buffer space reduces power consumption by eliminating redundant buffer operations. Instead of multiple buffers independently managing their own data storage and retrieval, a single buffer handles all levels, reducing the overall energy required for data management in the processing pipeline.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If each algorithm level uses dedicated buffer space, then data can be stored and retrieved at each level, but the overall delay of the image signal processor increases

Engineering Contradiction:
Improvedata storage and retrievalVSAvoidoverall processing delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent combines the buffer operations of multiple algorithm levels into a unified shared buffer space. This merging allows for more efficient data management and reduces the time required for data to be transferred between levels, as there are fewer buffer interfaces and synchronization points to navigate through.

Inventive Principle:
Principle #5Merging (Combining)

4Reliability

If multiple dedicated buffer spaces are allocated for each algorithm level, then each level can independently manage its data, but the device complexity increases

Engineering Contradiction:
Improveindependent data managementVSAvoidbuffer space configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the buffer space configurations of multiple algorithm levels into a single shared buffer space, reducing the complexity of buffer management. Instead of configuring and managing separate buffers for each level, the system uses one unified buffer, simplifying the overall device architecture while maintaining data integrity through coordinated access.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20250390975A1Point cloud processing method, image signal processor, radar chip and lidar
Publication Date: 2025.12.25 SUTENG INNOVATION TECHNOLOGY CO LTD
  • US20250390975A1 patent drawing
  • US20250390975A1 patent drawing
  • US20250390975A1 patent drawing

AI summary

A point cloud processing method, an image signal processor, a radar chip, and a LiDAR are provided. The point cloud processing method is applied to an image signal processor. The point cloud processing method is configured to run multi-level algorithms for point cloud processing. The multi-level algorithms include a first-level algorithm, a second-level algorithm, and a third-level algorithm that share a buffer space. The method includes: obtaining original point cloud data; starting the first-level algorithm to process the original point cloud data to obtain first point cloud data, and buffering the first point cloud data in a buffer space; and according to a delay difference between the second-level algorithm and the third-level algorithm, simultaneously inputting at least part of the first point cloud data and the second point cloud data into the third-level algorithm.