Lidar Sensor Readout Circuit Analog Memory Sampling
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Solution Overview
Problem
Existing Lidar sensors face challenges in cost-efficiency, reliability, and scalability, particularly in advanced driver assistance systems, due to complex logic requirements and potential defects in memory cells.
Innovation Solution
A Lidar sensor unit with a two-dimensional array of light sensitive detectors and a readout integrated circuit featuring analog memory cells connected via AND-gates for simplified sampling and selection, allowing for scalable and defect-tolerant design without complex address logic, and separate analog and digital components for efficient processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory cells with full address decoder logic are used, then memory functionality is achieved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts the address decoder logic from each individual memory cell and consolidates it into a shared row decoder and column decoder structure. Each memory cell is reduced to basic select inputs (row select and column select) without full address decoding capability, while the decoded address signals are generated externally and distributed to multiple cells simultaneously.
Solution Approach 2:
The memory array is segmented into multiple independently controllable blocks, each with its own row and column select lines. This segmentation allows the memory to be addressed in a distributed manner, reducing the complexity burden on individual cells while maintaining overall memory functionality through coordinated control of multiple segments.
2Reliability
If spare memory cell arrays are added for self-repair, then reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent makes the memory cell array universally addressable through the shared decoder structure, allowing any cell to be accessed or replaced flexibly. The same row and column select mechanism serves both normal operation and repair functions, eliminating the need for separate spare array control logic.
Solution Approach 2:
The simplified memory cell design with explicit row and column select inputs enables easier self-testing and self-repair capabilities. The universal addressing scheme allows defective cells to be identified and replaced by reconfiguring the select line connections without requiring complex additional repair circuitry.
3Adaptability or versatility
If modular design is used, then scalability is improved, but device complexity increases due to wiring requirements
Solution Approach 1:
The patent merges the address decoding functionality into shared external circuits that serve multiple memory modules simultaneously. The row decoder and column decoder are combined structures that distribute decoded addresses to multiple memory cell blocks, reducing the total wiring required compared to having separate decoders in each module.
Solution Approach 2:
The patent organizes memory cells in a two-dimensional array structure with row and column dimensions, allowing scalability through addition of rows and columns rather than through complex modular expansion. This dimensional organization enables systematic scaling while maintaining regular wiring patterns and shared control structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a compact, reliable, and cost-efficient Lidar sensor unit with improved yield and power management, capable of scaling without modifying existing components and effectively handling defective memory cells, thus enhancing reliability and scalability.
Implementation Method 1
a two dimensional array of a number of N light sensitive detectors converting impinging light into an electronic signal
Data Source
Figure 1~2
AI summary
A light detection and ranging (Lidar) sensor unit, comprising a light signal source, a two dimensional array of a number of N light sensitive detectors converting impinging light into an electronic signal, a readout integrated circuit and a processing unit, wherein the readout integrated circuit comprises a number of N memory units, each memory unit has an input connected to an output of one of said light sensitive detectors for receiving the electronic signal of the light sensitive detector, each memory unit comprises at least one array with I columns and J rows of analog memory cells, one column select line per column and one row select line per row for sampling the electronic signal received, each analog memory cell comprises an AND-gate a first input of the AND-gate being connected to the corresponding column select line and a second input of the AND-gate being connected to the corresponding row select line to select the analog memory cell for write and read.