Hardware Life-Cycle Management Circuit for Secure Failure Analysis
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Solution Overview
Problem
Modern processing systems face challenges in efficiently managing the life-cycle stages, particularly in advancing to the failure analysis stage without compromising security and safety, as existing methods require significant resources and risk accidental activation during normal operation.
Innovation Solution
A processing system architecture that includes a hardware configuration circuit to read and decode life-cycle data, a verification circuit to manage life-cycle advancement requests, and a write circuit to update non-volatile memory, allowing for controlled advancement to the failure analysis stage using a minimal set of resources and bypassing security layers, ensuring secure and safe operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of repair
If existing methods are used to advance to the failure analysis stage, then the system can perform diagnostic and testing processes, but the risk of accidental activation during normal operation increases and significant resources are required
Solution Approach 1:
The patent introduces a dedicated life-cycle management circuit as an intermediary component that mediates between the normal operational modes and the failure analysis stage. This separate hardware circuit independently manages life-cycle advancement without involving the microprocessor, thereby preventing accidental activation while enabling reliable diagnostic processes through a controlled intermediate management layer.
Solution Approach 2:
The system is segmented into distinct functional components: a microprocessor for normal operation and a separate life-cycle management circuit for stage advancement. This segmentation isolates the failure analysis activation logic from the main processing unit, reducing the risk of accidental activation during normal microprocessor operations while maintaining dedicated diagnostic capability.
2Ease of repair
If existing methods are used to manage life-cycle stages, then the system can advance to failure analysis stage, but significant processing resources are consumed
Solution Approach 1:
The life-cycle management circuit is designed as a self-service component that autonomously handles life-cycle stage advancement without requiring microprocessor intervention. The circuit independently reads life-cycle data from non-volatile memory, determines the current stage, and executes advancement logic using minimal dedicated resources, thereby conserving significant processing resources for their primary functions.
Solution Approach 2:
The life-cycle management functionality is extracted from the microprocessor and implemented as a separate, dedicated hardware circuit. This extraction removes the resource-intensive processing tasks from the microprocessor, allowing life-cycle stage advancement to occur with minimal processing resources while the microprocessor focuses on its core computational tasks.
3Reliability
If security layers are maintained during life-cycle advancement, then system security is preserved, but the ability to bypass security for failure analysis is limited
Solution Approach 1:
The system implements dynamic security management where the life-cycle management circuit can adaptively bypass security layers based on the current life-cycle stage. During normal operation stages, security remains fully active. When advancing to the failure analysis stage, the circuit dynamically modifies security settings to enable diagnostic access, thereby balancing security preservation with failure analysis capability through stage-dependent security policies.
Data Source
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AI summary
A processing system (10a) is described. The processing system (10a) comprises a microprocessor (1020), a hardware circuit (110) configured to change operation as a function of decoded life-cycle data (LC) and a non-volatile memory (104) configured to stored encoded life-cycle data (LCD). A hardware configuration circuit (108) is configured to read the encoded life-cycle data (LCD) from the non-volatile memory (104), decode the encoded life-cycle data (LCD) and provide the decoded life-cycle data (LC) to the hardware circuit (110). The processing system comprises also a reset circuit (116) configured to monitor an external reset signal received via a reset terminal (RP) and, in response to determining that the external reset signal has a first logic level, execute a reset phase (3002), a configuration phase (CP1) and a wait phase (3022), where the reset circuit (116) waits until the external reset signal has a second logic level. In particular, the processing system comprises also a communication interface (IF_JTAG) activated during the wait phase (3022) and configured to receive a request (REQ), and a hardware verification circuit (130) configured to generate a life-cycle advancement request signal (LCFA_REQ) when the request (REQ) comprises a given reference password (RK) and the reset circuit (116) is in the wait phase (3022). A write circuit (1044w) of the non-volatile memory (104) may thus write one or more bits of the encoded life-cycle data (LCD) stored in the non-volatile memory (104) when the life-cycle advancement request signal (LCFA_REQ) is set, thereby advancing the life-cycle to a given predetermined life-cycle stage.