Lift-off Thin Film Transistor Fabrication Eliminates Offset Regions
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Solution Overview
Problem
Conventional top-gate type thin film transistors suffer from offset regions due to critical dimension bias in wet etching, leading to increased parasitic resistance, ohmic contact resistance, and decreased current efficiency, which are not effectively addressed by high-power helium or hydrogen plasma conductorization.
Innovation Solution
A method of fabricating thin film transistors using a lift-off process to form self-aligned gate electrodes and insulating layers, eliminating offset regions and simplifying the fabrication process, with the option of forming source and drain electrodes in a single process and using high dielectric constant materials for improved electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wet etching is used to form gate electrodes, then the fabrication process is simple, but offset regions are created leading to increased parasitic resistance and decreased current efficiency
Solution Approach 1:
The patent applies preliminary action by forming the gate electrode pattern using photolithography and lift-off methods before depositing the active layer material. This pre-established pattern prevents offset region formation during subsequent processing, eliminating parasitic resistance issues while maintaining fabrication simplicity.
Solution Approach 2:
The lift-off method enables self-service by allowing the gate electrode pattern to self-align with the active layer boundaries through the photoresist mask. The pattern automatically defines the channel region limits, eliminating the need for separate alignment steps and preventing offset regions without increasing process complexity.
2Reliability
If high-power helium or hydrogen plasma conductorization is applied, then parasitic resistance is reduced, but the underlying offset region problem persists and fabrication complexity increases
Solution Approach 1:
The patent extracts and eliminates the offset region problem at its source by using photolithography-patterned gate electrodes that precisely define the channel boundaries. This removes the need for plasma conductorization steps, reducing both parasitic resistance and fabrication complexity simultaneously.
Solution Approach 2:
Instead of applying plasma treatment to reduce parasitic resistance after offset regions are formed, the patent inverts the approach by preventing offset region formation through precise photolithography patterning. This eliminates the need for additional conductorization steps and their associated complexity.
3Reliability
If multiple separate processes are used to form gate electrodes and insulating layers, then each layer can be optimized, but the fabrication process becomes complex and time-consuming
Solution Approach 1:
The patent merges the formation of gate electrodes and gate insulating layers into a single integrated process. The photoresist pattern serves as a mask for simultaneous deposition of both layers, maintaining layer optimization while significantly improving fabrication efficiency by reducing the number of separate processing steps.
Solution Approach 2:
The photoresist pattern performs multiple functions simultaneously: it defines the gate electrode pattern, defines the gate insulating layer pattern, and establishes the channel region boundaries. This multi-functionality enables optimization of multiple layers while maintaining high fabrication efficiency through a single patterning step.
Data Source
AI summary
The present application discloses a method of fabricating a thin film transistor. The method includes forming an active layer having a channel region, a source electrode contact region, and a drain electrode contact region, on a base substrate; forming a first photoresist layer on a side of the active layer distal to the base substrate, the first photoresist layer is formed in a region outside that corresponding to the channel region; forming an insulating material layer on a side of the first photoresist layer distal to the base substrate; forming a first conductive metal material layer on a side of the insulating material layer distal to the first photoresist layer; and removing the first photoresist layer, the insulating material layer, the first conductive metal material layer, in the region outside that corresponding to the channel region by a lift-off method.