Lifted LDPC Code Structure for Flexible Rates and Blocklengths

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Solution Overview

Problem

Current wireless communication systems face challenges in achieving high-performance, flexible, and compact low-density parity-check (LDPC) code designs that support large ranges of code rates, blocklengths, and granularity, while maintaining good error floor performance and high throughput, especially in next-generation wireless technologies like 5G NR.

Innovation Solution

The development of lifted LDPC code designs that enable fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extensions, with a focus on high parallelism and low description complexity, allowing for efficient encoding and decoding across various transmission rate regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional LDPC code designs are used, then implementation is simpler, but performance across large ranges of code rates and blocklengths deteriorates

Engineering Contradiction:
Improveerror correction performanceVSAvoidflexibility across code rates and blocklengths
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The LDPC code is segmented into an information bit sequence and a parity bit sequence generated through systematic encoding. The code structure is divided into information bits and parity bits, allowing flexible configuration of code rates by adjusting the ratio of information bits to total codeword length while maintaining reliable error correction through the separated parity checking mechanism.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The LDPC code design employs dynamic parameters including variable code rates (achieved by adjusting the number of information bits relative to codeword length), variable blocklengths (through different codeword lengths), and configurable granularity (via lifting operations on base graphs). This dynamic configurability allows the same LDPC code structure to adapt to diverse communication requirements while maintaining optimal error correction performance.

Inventive Principle:
Principle #15Dynamics

2Reliability

If high-performance LDPC code designs are implemented, then error correction capabilities improve, but description complexity increases

Engineering Contradiction:
Improveerror floor performanceVSAvoiddescription complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The LDPC code utilizes a base graph that can be copied and lifted multiple times to generate codes of different sizes and rates. Instead of designing unique complex parity check matrices for each code rate and blocklength, the same base graph structure is replicated and scaled through lifting operations, maintaining optimal error floor performance while significantly reducing description complexity since only the base graph needs to be stored and defined.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

A single LDPC base graph design serves multiple functions by supporting various code rates, blocklengths, and granularity requirements through systematic encoding and lifting operations. This universal base graph structure replaces the need for multiple specialized code designs, reducing overall system complexity while maintaining high error correction performance across diverse application scenarios.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If fine incremental redundancy IR-HARQ extension is enabled, then throughput performance improves, but code design complexity increases

Engineering Contradiction:
Improvethroughput performanceVSAvoidcode design complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The LDPC code is designed with preliminary structured parity bits and systematic encoding that facilitate incremental redundancy Hybrid ARQ (IR-HARQ). The parity bits are pre-calculated and organized in a manner that allows progressive transmission of additional redundancy information. This preliminary structuring enables fine incremental redundancy extensions where additional parity information can be transmitted in subsequent packets without requiring complete retransmission, thereby improving throughput while keeping the base code design relatively simple.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3852276A1Lifted low-density parity check (LDPC) codes
Publication Date: 2021.07.21 QUALCOMM INC
  • EP3852276A1 patent drawingFigure 1
  • EP3852276A1 patent drawingFigure 2
  • EP3852276A1 patent drawingFigure 3

AI summary

Certain aspects of the present disclosure can enable low-density parity-check, LDPC, code designs to support large ranges of rates, blocklengths, and granularity. Thereby, a method is disclosed comprising determining a low-density parity-check, LDPC, code base graph associated with a plurality of LDPC codes for a plurality of code rates and blocklengths, the LDPC base graph having a number of base graph columns corresponding to a maximum number of base information bits, determining a lifting size value for generating a lifted LDPC parity check matrix, PCM, generating the lifted LDPC PCM based on the base graph and the lifting size value, and generating an LDPC code based on the lifted LDPC PCM and an all zero matrix, wherein the LDPC code was shortened by either (i) removing one or more of the base graph columns or (ii) removing one or more lifted LDPC PCM columns, and wherein the shortening was based on at least one of: a desired code rate, lifting size value, or blocklength for a transmission.