Lifted LDPC Code Structure for Flexible IR-HARQ Rate Matching
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Solution Overview
Problem
Current wireless communication systems face challenges in achieving high-performance, flexible, and compact low-density parity-check (LDPC) code designs that support large ranges of code rates, blocklengths, and granularity, while maintaining good error floor performance and high throughput, especially in next-generation wireless technologies like 5G NR.
Innovation Solution
The development of lifted LDPC code designs that enable fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extensions, with a focus on high parallelism and low description complexity, allowing for efficient encoding and decoding across various transmission rate regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDPC code designs are used, then implementation is simpler, but performance and flexibility are insufficient for 5G NR requirements
Solution Approach 1:
The patent segments the LDPC code design into multiple components: base graphs with different configurations, rate matching patterns, and code rate regions. This segmentation allows the system to select appropriate code parameters for different transmission conditions, achieving high reliability without requiring a single complex code design to handle all scenarios.
Solution Approach 2:
The patent implements dynamic code rate adaptation by defining multiple code rate regions (e.g., 1/4, 2/5, 3/8, 1/2, 5/8, 3/4, 4/5, 5/6) and allowing selection of different base graphs and rate matching patterns based on channel conditions and traffic requirements. This dynamic adaptability achieves high reliability across varying conditions without fixing the code parameters.
2Adaptability or versatility
If LDPC codes support large ranges of code rates and blocklengths, then versatility improves, but description complexity increases
Solution Approach 1:
The patent creates universal base graphs that can serve multiple code rates and blocklengths through systematic rate matching. The base graphs are designed to support various code rates (from 1/4 to 5/6) and blocklengths (minimum 512 bits) using the same underlying structure, reducing description complexity while maintaining versatility.
Solution Approach 2:
The patent changes key parameters systematically: defining minimum blocklengths (512, 1024, 1536, 2048, 3072, 4096, 6144, 8192, 10240 bits), code rate regions, and base graph configurations. These parameter changes allow the same base graph structure to support diverse code rates and blocklengths, achieving versatility without proportionally increasing description complexity.
3Productivity
If high parallelism is implemented for high throughput, then productivity improves, but device complexity increases
Solution Approach 1:
The patent segments the encoding and decoding processes into parallelizable operations: base graph selection, rate matching pattern application, and bit sequence generation. This segmentation enables high parallelism in hardware implementation, achieving high throughput while managing complexity through modular processing stages.
Solution Approach 2:
The patent performs preliminary actions by pre-defining base graphs, rate matching patterns, and code rate regions before actual data transmission. These pre-configured structures enable rapid encoding and decoding operations during real-time communication, achieving high throughput without the overhead of dynamic parameter calculation during transmission.
Data Source
AI summary
Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.