LIGBT Manufacturing Using High Temperature Oxide Mini-Oxide Layer
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Solution Overview
Problem
Conventional methods for manufacturing lateral insulated-gate bipolar transistors (LIGBTs) introduce dislocations at the edge of the active region due to the stress differences between silicon nitride and the trench region during the Local Oxidation of Silicon (LOCOS) process, affecting the reliability of the product.
Innovation Solution
A method involving the use of high temperature oxide (HTO) as a mini-oxide layer, which is densified through thermal drive-in, reducing the surface electric field and eliminating dislocations by stabilizing the etching process, ensuring reliable volume production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon nitride is used as a hard mask to grow silicon dioxide via LOCOS technology, then the surface electric field of the LDMOS can be reduced, but a large number of dislocations are introduced on the edge of the active region
Solution Approach 1:
The patent changes the material parameter from silicon nitride to high temperature oxide (HTO), which has different stress characteristics. This parameter change eliminates the stress-induced dislocations at the active region edge while maintaining the electric field reduction function, thereby resolving the contradiction between reliability and harmful factors
Solution Approach 2:
The patent employs a temporary HTO layer that serves as a sacrificial structure during manufacturing. This layer is later removed after serving its purpose of reducing surface electric field, avoiding permanent dislocation structures while achieving the desired electrical characteristics
2Object-generated harmful factors
If HTO is used as mini-oxide layer, then dislocations are eliminated, but the wet etching rate of HTO is high which affects etching control
Solution Approach 1:
The patent applies a preliminary thermal drive-in process to densify the HTO layer before subsequent etching operations. This preliminary action reduces the wet etching rate of HTO by altering its physical structure, thereby improving etching control stability while maintaining the dislocation-free characteristic
Solution Approach 2:
The patent changes the physical state parameter of HTO through thermal drive-in, transforming it from a less dense to a denser structure. This parameter change significantly reduces the wet etching rate while preserving the material's ability to function as an effective mini-oxide layer without introducing dislocations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces dislocations at the edge of the active region, stabilizes the etching process, and ensures the reliability and efficiency of LIGBT production, allowing for successful volume production without introducing defects.
Implementation Method 1
performing a thermal drive-in to the wafer, and performing photolithography and etching to the HTO film to form a mini-oxide layer
Implementation Method 2
by using HTO, which has a relatively less stress than silicon nitride, as the mini-oxide that reduce the surface electric field of the LIGBT, no dislocation will be introduced on the edge of the active region
Data Source
AI summary
The present invention relates to a method for manufacturing a laterally insulated-gate bipolar transistor, comprising: providing a wafer having an N-type buried layer (10), an STI (40), and a first N well (22)/a first P well (24) which are formed successively from above a substrate; depositing and forming a high-temperature oxide film on the first N well (22) of the wafer; performing thermal drive-in on the wafer and performing photoetching and etching on the high-temperature oxide film to form a mini oxide layer (60); performing photoetching and ion implantation so as to form a second N well (32) inside the first N well (22) and second P wells (34) inside the first N well (22) and the first P well (24); then successively forming a gate oxide layer and a polysilicon gate (72), wherein one end of the gate oxide layer and the polysilicon gate (72) extends onto the second P well (34) inside the first N well (22), and the other end extends onto the mini oxide layer (60) on the second N well (32); and photoetching and injecting N-type ions between the mini oxide layer (60) and the STI (40) adjacent to the mini oxide layer (60) to form a drain electrode, and at the same time forming a source electrode (51) inside the second P well (34).