Light-to-Digital Converter with Stepped Reference Integration
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Solution Overview
Problem
Existing light-to-digital converter arrangements face challenges in accurately measuring low light conditions due to high noise and accuracy issues, as they often rely on scaling down integration parameters which increase noise and reduce accuracy.
Innovation Solution
A light-to-digital converter arrangement using a time integrator with a fixed integration range and an adjustable reference signal incremented in discrete steps, combined with an adaptive binning algorithm to adjust step sizes and account for initial integration signal values, allowing for higher gains without reducing integration voltages or capacitors, thus maintaining low noise and good linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the integration range and reference capacitors are made smaller to achieve higher gains, then the gain increases, but noise and accuracy deteriorate
Solution Approach 1:
The patent divides the integration process into multiple discrete steps, where the integration range is segmented into multiple levels. Instead of using a single large integration range that requires scaling, the system performs multiple smaller integration steps, each with its own comparator trigger, to achieve the same overall gain without the noise penalties of scaled-down components.
Solution Approach 2:
The patent introduces dynamic adjustment of the reference voltage level during the integration process. The reference voltage is incremented in discrete steps based on comparator triggers, allowing the system to adaptively optimize the integration range for different light conditions while maintaining component sizes that minimize noise.
2Power
If the integration range and reference capacitors are made smaller to achieve higher gains, then the gain increases, but noise increases
Solution Approach 1:
The integration range is segmented into multiple discrete levels, allowing the system to achieve high overall gain through multiple small steps rather than one large step. This segmentation enables the use of larger reference capacitors that produce less noise, while still achieving the required gain through cumulative integration steps.
Solution Approach 2:
The patent performs multiple integration cycles, each integrating for a portion of the total required gain. By accumulating results from multiple partial integration cycles, the system achieves the desired high gain while each individual cycle uses larger components that generate less noise.
3Device complexity
If a fixed integration range is used, then the circuit design is simplified, but the ability to adapt to different light conditions is reduced
Solution Approach 1:
The patent introduces dynamic adjustment of the reference voltage level during the integration process. The reference voltage is incremented in discrete steps based on comparator triggers, allowing the system to adaptively optimize the integration range for different light conditions while maintaining component sizes that minimize noise.
Solution Approach 2:
The system uses feedback from the comparator trigger events to dynamically adjust the reference voltage level. When the integrator output reaches the upper threshold, the comparator triggers and increments the reference voltage, creating a feedback mechanism that automatically adapts the integration range to the current light conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables increased gain with improved linearity and low noise, allowing for higher system gains without the need for smaller capacitors or integration ranges, effectively addressing the limitations of existing technologies in low light conditions.
Implementation Method 1
a sensor device (14) connected to the sensor input (11) and providing a sensor signal; Integrating charge from the sensor device
Data Source
Figure 1
Figure 2~3
Figure 4
AI summary
A method for light-to-digital conversion comprises setting a time integrator circuit (10) into a reference condition and starting to integrate charge from a sensor device (PD) for the duration of an integration time (Atime). An integration signal (OPOUT) is generated and is indicative of the integrated charge. The integration signal (OPOUT) is compared with an adjustable reference signal (Vref). A first count (C1) is generated when the comparison indicates that the integration signal (OPOUT) has reached an integration range (Vdiff), wherein the integration range (Vdiff) is defined by a low and a high voltage (VL, VH). A second count (C2) is generated when the comparison indicates that the integration signal (OPOUT) has reached the adjustable reference signal (Vref). The adjustable reference signal (Vref) is incremented in discrete steps when a second count (C2) has been generated. Then, the time integrator circuit (10) is reset into the reference condition, when the comparison indicates that the integration signal (OPOUT) has reached the integration range (Vdiff). The generated first counts is collected as first count signal (CT_LOUT) and the generated second counts are collected as second count signal (CT_COUT). Finally, a digital output signal (ADC_OUT) is generated depending on the first count signal (CT_LOUT) and the second count signal (CT_COUT).