Semiconductor Light-Emitter Wiring Layout for Low Inductance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor light-emitting devices face challenges with inductance issues due to wiring configurations, which affect the performance and accuracy of applications like LIDAR systems, where reducing inductance is crucial for faster output waveforms and precise distance measurement.
Innovation Solution
The semiconductor light-emitting device incorporates a multilayer board with specific wiring patterns and element arrangements, where the light-emitting element, switching element, and capacitor are electrically connected by both front and back surface wiring patterns, forming current paths that cancel out magnetic flux, thereby reducing inductance. This configuration includes overlapping current paths on the board's surface and backside to minimize magnetic flux interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the light-emitting element, switching element, and capacitor are electrically connected using wirings arranged separately on the board, then the device structure is simple and easy to manufacture, but inductance increases due to the wiring paths
Solution Approach 1:
The patent transitions from planar wiring arrangement to three-dimensional stacked arrangement. The light-emitting element, switching element, and capacitor are arranged in different layers (first through fourth substrates) with wiring patterns on both front and back surfaces, creating vertical and horizontal current paths that reduce inductance while maintaining manufacturability through standard multilayer PCB techniques.
Solution Approach 2:
The device is divided into multiple functional modules arranged in specific spatial relationships: light-emitting element module, switching element module, and capacitor module, each mounted on different substrates. This segmentation allows optimized current path design where first and second wiring patterns create overlapping current loops that cancel magnetic flux, reducing inductance without complicating manufacturing.
2Speed
If the wiring patterns are arranged to reduce inductance by forming overlapping current paths, then inductance decreases and output waveform speed improves, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent uses vertical stacking of substrates (first, second, third, fourth substrates) with wiring patterns on both front and back surfaces to create three-dimensional current paths. This spatial arrangement reduces inductance by forming tight overlapping loops while maintaining manageable device complexity through systematic layering and standardized mounting procedures.
Solution Approach 2:
The first and second wiring patterns are designed to form overlapping current paths that merge in space, creating canceling magnetic flux regions. The light-emitting element, switching element, and capacitor are electrically connected through both front-surface and back-surface wiring, merging multiple current paths into a unified low-inductance configuration that improves output waveform speed without excessive complexity.
3Measurement precision
If the elements are arranged in specific directions to cancel magnetic flux, then inductance reduces and measurement precision improves, but the manufacturing precision requirements increase
Solution Approach 1:
The patent arranges elements and wiring patterns in three-dimensional space across multiple substrates with specific directional orientations. The first wiring pattern and second wiring pattern are configured at different levels and angles to create overlapping current paths that cancel magnetic flux, reducing inductance for improved LIDAR measurement precision while using standard manufacturing tolerances through systematic spatial design.
Solution Approach 2:
The device employs asymmetric arrangement of elements and wiring patterns where the first and second wiring patterns have different geometries and orientations on front and back surfaces. This asymmetric design optimizes magnetic flux cancellation for low inductance while accommodating standard manufacturing variations, achieving high measurement precision without excessive manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces inductance in the semiconductor light-emitting device, leading to faster output waveforms and improved accuracy in distance measurement applications, such as LIDAR, by canceling out magnetic flux and enhancing the cancellation of magnetic flux regions.
Implementation Method 1
the second wiring pattern is configured to form a second current path through which a second current flows in an opposite direction to a direction in which the first current flows through the first current path, the second current path overlapping the first current path when viewed in the thickness direction of the board
Data Source
AI summary
A semiconductor light-emitting device includes: a board including a front surface, a back surface facing an opposite side of the front surface, a first wiring pattern formed on the front surface, and a second wiring pattern formed on the side of the back surface with respect to the first wiring pattern; and a light-emitting element, a switching element, and a capacitor, which are electrically connected to one another by both the first wiring pattern and the second wiring pattern. Among the light-emitting element, the switching element, and the capacitor, a first predetermined element and a second predetermined element are arranged in a first direction and the second predetermined element and a third predetermined element are arranged in a second direction. The second wiring pattern forms a second current path opposite to a direction of a first current path. The second current path overlaps the first current path.