Light Receiving Circuit Pulse Width Distortion Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In light receiving circuits, the increase in input pulse optical signal level leads to increased current, resulting in delay time and output pulse width distortion, which is not effectively addressed by existing technologies.

Innovation Solution

A light receiving circuit design incorporating a light receiving element, a transimpedance amplifier, a delay circuit, and a comparator with specific MOSFET configurations and gate length-to-width ratios to control current and reduce pulse width distortion, including a second MOSFET with delayed gate voltage and a third MOSFET for reference voltage, effectively managing drain currents to minimize distortion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the input level of the pulse optical signal is increased, then the current of the light receiving circuit increases, but the delay time increases and output pulse width distortion increases

Engineering Contradiction:
ImprovecurrentVSAvoidoutput pulse width distortion
Core Design Contradiction:
PowerVSManufacturing precision

Solution Approach 1:

The patent segments the light receiving circuit into multiple parallel paths: a first light receiving element connected directly to the output, and a second light receiving element connected through a delay circuit. This segmentation allows different portions of the input signal to be processed through different paths, with the delay circuit compensating for timing differences, thereby reducing output pulse width distortion while maintaining high current capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The delay circuit acts as an intermediary element that introduces a controlled time delay to the signal path containing the second light receiving element. This intermediary delay compensates for the inherent timing differences between parallel signal paths, enabling the circuit to maintain low pulse width distortion even when operating at high current levels with increased input optical signal strength.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the current of the light receiving circuit is increased to handle higher optical signal levels, then the signal processing capability improves, but the delay time increases

Engineering Contradiction:
Improvesignal processing capabilityVSAvoiddelay time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The circuit segments the signal processing into parallel paths with different delay characteristics. The first light receiving element provides a fast direct path, while the second light receiving element with delay circuit provides an additional processing path. This segmentation enables high signal processing capability through increased current handling while the deliberate delay compensation maintains overall timing accuracy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the timing parameter of the signal path by introducing a controlled delay through the delay circuit. This parameter change (adding delay) is compensated by the parallel structure, allowing the circuit to process higher current signals without net increase in overall delay, thus improving productivity without sacrificing time efficiency.

Inventive Principle:
Principle #35Parameter changes

3Loss of time

If conventional light receiving circuits are used to maintain low delay time, then the delay time remains low, but pulse width distortion cannot be effectively reduced

Engineering Contradiction:
Improvedelay timeVSAvoidpulse width distortion
Core Design Contradiction:
Loss of timeVSManufacturing precision

Solution Approach 1:

The patent divides the light receiving circuit into multiple parallel paths with different characteristics. By segmenting the circuit this way, it achieves low delay time through the direct first path while simultaneously reducing pulse width distortion through the compensated second path with delay circuit, resolving the contradiction between these two parameters.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The delay circuit provides a feedback mechanism that compensates for timing differences in the parallel signal paths. This feedback approach allows the circuit to maintain low overall delay while actively correcting pulse width distortion, achieving both low delay time and reduced distortion that conventional single-path circuits cannot achieve.

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design significantly reduces pulse width distortion across a wide range of optical signal inputs without increasing delay time, eliminating the need for high power consumption automatic threshold adjustment circuits.

Implementation Method 1

a light receiving element (10) which converts a received optical signal into a current signal

Methodology Applied
Scientific EffectPhotoelectric effect: Photoelectric Effect

Data Source

PatentUS9153708B2Light receiving circuit and photocoupler
Publication Date: 2015.10.06 KK TOSHIBA
  • US9153708B2 patent drawing
  • US9153708B2 patent drawing
  • US9153708B2 patent drawing

AI summary

A light receiving circuit includes a light receiving element, a transimpedance amplifier, a delay circuit and a comparator. The transimpedance amplifier is configured to convert the current signal into a first voltage. The comparator includes first to third current control elements each including first to third electrodes and configured to control current of the third electrode by voltage of the second electrode. The first voltage is inputted to the second electrode of the first current control element. Output voltage of the delay circuit is inputted to the second electrode of the second current control element. A second voltage is inputted to the second electrode of the third current control element. The comparator is configured to compare output current of the first current control element with sum of output current of the second current control element and output current of the third current control element.