Light-Sensing Transistor With Direct Metal-Semiconductor Junction
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Solution Overview
Problem
The existing thin film transistor (TFT) manufacturing process for light sensing devices faces challenges in achieving high light sensitivity due to incompatibility with low temperature poly-silicon (LTPS) processes, particularly because the doping of n-plus material is not compatible with these processes.
Innovation Solution
A light sensing transistor design where the metal layer is in direct contact with the semiconductor layer without an intermediating n-plus layer, allowing for better compatibility with various manufacturing processes and utilizing chemical vapor deposition methods to deposit the semiconductor layer, which enhances light sensitivity through light-induced barrier lowering (LIBL) at the junction interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an intermediating n-plus layer is used between metal layer and semiconductor layer, then manufacturing process compatibility is improved, but light sensitivity deteriorates
Solution Approach 1:
The patent removes the intermediating n-plus layer from the structure, allowing direct contact between the metal layer and semiconductor layer. This extraction of the problematic layer resolves the contradiction by eliminating the barrier to light-induced carrier generation while maintaining manufacturing feasibility through direct deposition processes.
Solution Approach 2:
The patent employs a composite structure where the metal layer and semiconductor layer are directly interfaced, creating a heterostructure that leverages the unique properties of both materials. This direct interface enables efficient light-induced barrier lowering (LIBL) effect while maintaining process compatibility through careful material selection and deposition parameter optimization.
2Measurement precision
If direct contact between metal layer and semiconductor layer is implemented, then light sensitivity is improved, but manufacturing process compatibility worsens
Solution Approach 1:
The patent optimizes critical parameters including deposition temperatures, layer thicknesses, and material compositions to enable direct metal-semiconductor contact. By carefully controlling these parameters, the invention achieves the desired direct interface for enhanced light sensitivity while maintaining compatibility with existing manufacturing processes through parameter adjustment rather than process redesign.
3Reliability
If n-plus material doping is used, then device performance is improved, but compatibility with low temperature poly-silicon process deteriorates
Solution Approach 1:
The patent replaces the chemical doping process (n-plus material implantation) with a physical deposition approach where the metal layer is directly deposited onto the semiconductor layer. This substitution eliminates the need for high-temperature doping processes, thereby maintaining compatibility with low temperature poly-silicon manufacturing while achieving enhanced device performance through the direct metal-semiconductor interface and LIBL effect.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves light sensitivity and compatibility with different manufacturing processes, enabling higher linearity and sensitivity to incident light, while also allowing for effective shielding of noise from the backside light, thus enhancing the signal-to-noise ratio.
Implementation Method 1
utilizing chemical vapor deposition methods to deposit the semiconductor layer, which enhances light sensitivity through light-induced barrier lowering (LIBL) at the junction interface
Implementation Method 2
utilizing chemical vapor deposition methods to deposit the semiconductor layer
Data Source
AI summary
A light sensing transistor is provided. The light sensing transistor includes a substrate, a metal layer, and a semiconductor layer. The metal layer and the semiconductor layer are disposed on the substrate. The metal layer has a first metal structure and a second metal structure. The first metal structure and the second metal structure are in direct contact with the semiconductor layer.


