Light-Sensitive Sensor Layout for Lower Dark Current Noise
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Solution Overview
Problem
Current light-sensitive sensors in display panels have poor noise immunity and sensitivity, which reduces the accuracy of fingerprint recognition.
Innovation Solution
A light-sensitive sensor design featuring a third metal layer with a second gate, a second insulating layer, a second semiconductor layer with conductive portions at both ends, and a fourth metal layer including a second source and drain, where a gap area between the second gate and the second source and/or drain reduces dark current, enhancing anti-noise performance and sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional light-sensitive sensor structure is used, then device complexity is reduced, but noise immunity and sensitivity deteriorate
Solution Approach 1:
The sensor structure is divided into multiple functional layers including a first substrate, first insulating layer, first semiconductor layer with first gate, second insulating layer, second semiconductor layer with second gate, and third insulating layer. This segmentation allows each layer to perform specific functions, improving noise immunity and sensitivity while managing complexity through modular design
Solution Approach 2:
The patent implements a nested structure where the first semiconductor layer and first gate are embedded within insulating layers, and the second semiconductor layer and second gate are similarly nested. This nested arrangement allows compact integration of multiple functional elements, achieving improved performance without excessive increase in overall device complexity
2Measurement precision
If conventional light-sensitive sensor structure is used, then manufacturing process is simplified, but sensitivity deteriorates
Solution Approach 1:
The patent forms insulating layers and semiconductor layers in a predetermined sequence with specific doping concentrations and thicknesses before final device assembly. This preliminary structuring ensures optimal sensitivity characteristics are built-in during manufacturing, allowing standard fabrication processes to achieve high-performance results
Solution Approach 2:
The patent optimizes sensitivity by controlling specific parameters including the doping concentration of the second semiconductor layer (1×10^19 to 1×10^21 atoms/cm³), the thickness of insulating layers (50-200 nm), and the gate structure dimensions. These parameter optimizations enable high sensitivity while maintaining compatibility with existing manufacturing processes
3Object-generated harmful factors
If gate fully covers semiconductor layer, then control efficiency is improved, but dark current increases
Solution Approach 1:
The patent applies different structural qualities to different regions: the second gate partially overlaps the second semiconductor layer rather than fully covering it, creating a localized field effect that controls dark current generation at the interface while maintaining sensitivity in the active sensing region. This local quality differentiation resolves the contradiction between dark current suppression and overall sensor performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The improved design enhances anti-noise performance and sensitivity of the light-sensitive sensor, leading to increased accuracy of fingerprint recognition.
Implementation Method 1
use different intensity of light reflected from valleys and ridges of a fingerprint into a sensing area of the display panel, and to convert different light signals into electrical signals
Data Source
AI summary
A light-sensitive sensor, an array substrate, and an electronic equipment are provided. The light-sensitive sensor includes a third metal layer, a second semiconductor layer, and a fourth metal layer. The third metal layer includes a second gate. The second semiconductor layer includes conductive portions, and the conductive portions are disposed at both ends of the second semiconductor layer. The fourth metal layer disposed on the second semiconductor layer, and the fourth metal layer includes a second source and a second drain.