Light Sensor Pixel Comparator Layout With Fewer MOS Transistors
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Solution Overview
Problem
Existing light sensors face challenges in compactness and dispersion of comparators, requiring more connections in stacked semiconductor levels, which affects their efficiency and precision.
Innovation Solution
A light sensor design with each pixel comprising a comparator that includes a first and second channel MOS transistor connected in series, a current source, a photodiode, and a reset switch, implemented in a stack of semiconductor layers with fewer connections through hybrid bonding, using a comparator with fewer MOS transistors and improved precision due to a shaping circuit and voltage ramps for comparison.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional comparator with multiple MOS transistors is used in each pixel, then the comparison function is achieved, but the pixel area and device complexity increase
Solution Approach 1:
The patent extracts and eliminates redundant MOS transistors from the conventional comparator circuit. By using a simplified comparator architecture with fewer transistors, the design achieves the same comparison function without the complexity of traditional differential pairs, directly reducing device complexity while maintaining measurement precision
Solution Approach 2:
The patent changes the operational parameters of the comparator by using voltage ramps instead of traditional voltage comparisons. This parameter change allows the use of fewer transistors while achieving accurate light detection, resolving the contradiction between precision and complexity
2Reliability
If more hybrid bonding connections are used in stacked semiconductor levels, then the connectivity between layers is improved, but the manufacturing complexity and production time increase
Solution Approach 1:
The patent extracts and removes the need for certain hybrid bonding connections between stacked semiconductor levels by integrating functions directly into the pixel structure. This reduction in required connections simplifies manufacturing while maintaining reliable electrical connectivity where essential
Solution Approach 2:
The patent merges multiple functions into fewer semiconductor layers, reducing the total number of inter-layer connections required. By combining photodetection, comparison, and signal processing functions in an integrated manner, the design reduces manufacturing complexity while maintaining system reliability
3Measurement precision
If the comparator occupies more surface area, then the comparison accuracy is improved, but the pixel compactness is reduced
Solution Approach 1:
The patent changes the comparison method from traditional voltage-based comparison requiring large transistor structures to ramp-based comparison that achieves high accuracy in a compact area. This parameter change enables high comparison accuracy without increasing pixel surface area
Solution Approach 2:
The patent replaces the mechanical/transistor-based comparison mechanism with an electrical ramp signal approach. This substitution eliminates the need for large transistor structures while maintaining or improving comparison accuracy, achieving compact pixel design
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design results in a more compact and precise light sensor with reduced dispersion, achieving efficient light detection and comparison, and eliminating the need for correlated double sampling, while maintaining equivalent consumption and occupied surface area.
Implementation Method 1
at least one photodiode coupled to a gate of the first transistor
Data Source
Figure 1~2
Figure 3~4
AI summary
The present description relates to a light sensor (4) in which each pixel comprises: first and second MOS transistors (T1, T2) connected in series by their sources (S), a gate of the second transistor (T2) receiving a comparison voltage (Vcmp); a first current source (104) in series with said transistors (T1, T2) between a first supply potential (GND) and a second supply potential (VDD2); a third MOS transistor (T3) and a second current source (108) in series between a third supply potential (GND) and a fourth supply potential (VDD1), the third transistor (T3) having a gate connected to a node (106) connecting the first current source (104) to the first and second transistors (T1, T2); a photodiode (PD) coupled to a gate of the first transistor (T1); and a switch (RST) connected to the gate of the first transistor (T1).