Light-Emitting Signal Circuit With Delayed Clocks for Stable TFT Fall Time
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Solution Overview
Problem
The threshold voltage shift in driving thin film transistors (TFTs) affects the output waveform of enhanced pulse width modulators (EPWMs) over time, leading to changes in fall time, which can cause optical defects in display devices.
Innovation Solution
A light-emitting signal generating circuit is designed with specific transistor and capacitor configurations that allow the TFTs to operate in the linear region quickly, using delayed clock signals to minimize the impact of threshold voltage shifts, ensuring stable waveform performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the driving TFT operates in saturation region for extended periods, then the transistor can maintain stable operation, but the threshold voltage shifts over time causing fall time changes and optical defects
Solution Approach 1:
The patent dynamically switches the driving TFT between saturation and linear regions using a two-phase clock signal system. During the first phase (first clock signal), the TFT operates in saturation for stable operation. During the second phase (second clock signal with delayed falling edge), the TFT operates in linear region to reset threshold voltage and maintain consistent fall time. This dynamic region switching resolves the contradiction between stable operation and fall time consistency.
Solution Approach 2:
The patent implements periodic threshold voltage reset by using alternating clock phases. The first clock signal enables normal saturation operation, while the second delayed clock signal periodically forces linear region operation to reset threshold voltage. This periodic action prevents cumulative threshold voltage shift and maintains consistent fall time across multiple display frames.
2Speed
If the falling edge of the second clock signal occurs before the first clock signal, then the linear region operation can be established earlier, but the overlapping low level period cannot be achieved causing incomplete threshold voltage reset
Solution Approach 1:
The patent delays the falling edge of the second clock signal relative to the first clock signal, creating a preliminary period where both signals are in low level overlap. This preliminary timing arrangement ensures that the linear region operation is properly established and threshold voltage is completely reset before the next saturation operation begins, preventing incomplete reset conditions.
Solution Approach 2:
The patent uses the overlapping low level period of the two clock signals as an intermediary mechanism. This overlap period acts as a buffer that ensures complete threshold voltage reset by maintaining linear region operation long enough to fully discharge the storage node, bridging the transition between saturation and linear regions reliably.
3Manufacturing precision
If a delay circuit is added to delay the first clock signal, then the falling edge timing can be controlled, but the circuit complexity increases
Solution Approach 1:
The patent combines the delay function with the existing clock signal generation circuitry by using a second clock signal that is naturally delayed relative to the first clock signal. Instead of adding a separate delay circuit, the design merges the timing control function into the dual-clock architecture, achieving precise falling edge timing control without significant additional circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed circuit configuration reduces the influence of threshold voltage shifts on TFTs, maintaining consistent light-emitting signal quality and preventing optical defects by keeping TFTs in the linear region, thus stabilizing the fall time of the output waveform.
Implementation Method 1
the first capacitor includes a first terminal for receiving a second clock signal and a second terminal coupled to the second terminal of the first transistor and the gate terminal of the second transistor
Data Source
AI summary
A light-emitting signal generating circuit includes a first transistor, having a first terminal for receiving a first light-emitting signal, a gate terminal for receiving a first clock signal, and a second terminal that generates a control signal; a second transistor that has a first terminal for receiving a first reference voltage, a gate terminal, and a second terminal for outputting a second light-emitting signal; a first capacitor having a first terminal for receiving a second clock signal, and a second terminal coupled to the second terminal of the first transistor and a gate terminal of the second transistor, wherein a low level period of the first clock signal partially overlaps with a low level period of the second clock signal, and a falling edge of the second clock signal lags behind a falling edge of the first clock signal.