Lightweight Address Translation for Page Migration
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Solution Overview
Problem
In processing systems with non-uniform memory access, duplicating or migrating pages to improve performance introduces overhead due to the need for resource-intensive operating system interrupts and additional address translation steps, which increase memory latency.
Innovation Solution
A lightweight address translation mechanism that inserts entries into the translation lookaside buffer (TLB) to map virtual addresses to physical addresses in a destination memory without modifying page tables, using a duplicate translation table (DTT) to extend the lifetime of duplicate or migrated pages and maintain cache coherence, thereby avoiding the overhead of updating page tables and additional translation levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If page duplication or migration is implemented to improve processing system performance, then memory access speed is improved, but system overhead increases due to operating system interrupts and additional address translation steps
Solution Approach 1:
The invention segments the address translation process by introducing a dedicated duplicate translation table (DTT) that handles translations for duplicated or migrated pages separately from the main page table. This segmentation allows the system to bypass the resource-intensive operating system interrupt mechanism that would otherwise be required to update page tables, thereby reducing system overhead while maintaining accurate address translations for performance-critical memory accesses.
Solution Approach 2:
The duplicate translation table (DTT) acts as an intermediary structure between the virtual address space and the physical memory locations of duplicated or migrated pages. Instead of modifying the main page table through operating system interrupts, the DTT provides a lightweight, hardware-maintained translation layer that directly maps virtual addresses to the new physical locations, eliminating the need for costly OS intervention and reducing system overhead time.
2Measurement precision
If page tables are updated to maintain address translation accuracy, then translation accuracy is improved, but processing time increases due to resource-intensive operating system interrupts
Solution Approach 1:
The invention segments the translation management responsibility by creating a separate duplicate translation table (DTT) dedicated to handling translations for duplicated or migrated pages. This segmentation allows the system to maintain translation accuracy for these specific pages without triggering resource-intensive operating system interrupts, as the DTT can be updated through lightweight hardware mechanisms while the main page table remains unchanged.
Solution Approach 2:
The invention creates a copy of the translation information in the duplicate translation table (DTT) that mirrors the functionality of the main page table for duplicated or migrated pages. This copying approach allows the system to maintain accurate translations by duplicating the relevant translation entries in the DTT, enabling fast, interrupt-free updates while preserving translation accuracy for the affected pages.
3Adaptability or versatility
If additional address translation levels are introduced to support page duplication, then translation flexibility is improved, but memory latency increases due to extra translation steps
Solution Approach 1:
The invention segments the translation process by introducing a dedicated duplicate translation table (DTT) that handles translations for duplicated or migrated pages in a single, direct step. This segmentation provides translation flexibility for page duplication operations while avoiding the need for multiple sequential translation steps, as the DTT is specifically optimized to provide direct virtual-to-physical address mapping for the affected pages, thereby reducing memory latency.
4Productivity
If lightweight address translation is used to reduce overhead, then system efficiency is improved, but cache coherence maintenance becomes more complex
Solution Approach 1:
The duplicate translation table (DTT) serves as an intermediary structure that simplifies cache coherence maintenance by providing a dedicated, hardware-managed translation layer for duplicated or migrated pages. This intermediary approach allows the system to maintain cache coherence through lightweight hardware mechanisms associated with the DTT, avoiding the need for complex software-based coherence protocols, thereby improving system efficiency while managing complexity through structured design.
Data Source
AI summary
A first processor is configured to detect migration of a page from a second memory associated with a second processor to a first memory associated with the first processor or to detect duplication of the page in the first memory and the second memory. The first processor implements a translation lookaside buffer (TLB) and the first processor is configured to insert an entry in the TLB in response to the duplication or the migration of the page. The entry maps a virtual address of the page to a physical address in the first memory and the entry is inserted into the TLB without modifying a corresponding entry in a page table that maps the virtual address of the page to a physical address in the second memory. In some cases, a duplicate translation table (DTT) stores a copy of the entry that is accessed in response to a TLB miss.