Lightweight Interrupts for Floating Point Exceptions via BESCR Enable Bit
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Solution Overview
Problem
Processing of floating point exceptions in computer systems often results in performance delays due to the need for supervisor intervention or polling of status registers, which can disrupt the sequential operation of system functions.
Innovation Solution
Implementing lightweight interrupts that allow the application to handle floating point exceptions directly through a notification mechanism, eliminating the need for supervisor intervention and polling by using a control register with specific bits to enable or disable these interrupts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If supervisor software handles floating point exceptions through traditional interrupts, then exception handling is reliable and controlled, but system performance deteriorates due to processing delays
Solution Approach 1:
The patent segments exception handling into two paths: traditional supervisor interrupts for critical exceptions and lightweight interrupts for floating point exceptions. This segmentation allows floating point exceptions to be handled at the application level without full supervisor intervention, improving performance while maintaining reliability for other exception types.
Solution Approach 2:
The patent introduces a lightweight interrupt mechanism as an intermediary between floating point exceptions and application handlers. This intermediary allows exceptions to be notified to applications without requiring full supervisor software involvement, reducing processing delays while maintaining controlled exception handling.
2Productivity
If application polls floating point status register to check for exceptions, then exception handling is efficient and avoids supervisor interrupts, but system performance deteriorates due to polling overhead
Solution Approach 1:
The patent implements a feedback mechanism where the floating point unit sets status bits in a control register when exceptions occur. The application can check these status bits without polling, and the lightweight interrupt mechanism provides automatic notification when exceptions are pending, eliminating the need for continuous polling while maintaining efficiency.
Solution Approach 2:
The patent prepares the exception status bits in advance in the control register before the application needs to check for exceptions. The floating point unit continuously monitors and sets these bits when exceptions occur, so the application only needs to check the pre-prepared status rather than continuously polling, reducing time loss.
3Reliability
If traditional interrupt mechanism is used for floating point exceptions, then exception handling is controlled and reliable, but device complexity increases due to supervisor intervention requirements
Solution Approach 1:
The patent segments the interrupt handling complexity by creating a lightweight interrupt path that bypasses the full supervisor software stack for floating point exceptions. This segmentation reduces device complexity by eliminating unnecessary supervisor involvement while maintaining reliability through controlled status bits and interrupt mechanisms.
Data Source
AI summary
Embodiments relate to lightweight interrupts for floating point exceptions. An aspect includes, based on an exception occurring in a floating point unit of a processor during execution of an application, sending a lightweight interrupt corresponding to the exception to the application; and handling the exception by an exception handler of the application.