Error Correction Circuit Using Likelihood-Guided Row and Column Decoding
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Solution Overview
Problem
High-performance error correction methods in communication systems, particularly in coherent optical communication, lead to increased circuit scale and power consumption due to the need for advanced processing and longer coding units to handle burst errors effectively.
Innovation Solution
An error correction circuit and method that combines first error correction processing in the row direction with second error correction processing in the column direction, using likelihood calculations to identify and correct bits, thereby reducing circuit scale while maintaining transmission characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If soft decision error correction method is used to improve transmission characteristics, then error correction capability is enhanced, but circuit scale and power consumption are increased
Solution Approach 1:
The error correction process is divided into two distinct stages: first error correction processing and second error correction processing. The first stage performs comprehensive error correction on all rows, while the second stage selectively processes only specific rows identified as having errors. This segmentation allows the system to achieve high error correction capability without requiring all circuit components to operate at full capacity simultaneously, thus reducing overall circuit scale and power consumption.
Solution Approach 2:
The patent applies different processing qualities to different rows of data based on their error characteristics. Rows identified through the first error correction processing as containing errors receive intensive second error correction processing, while rows without errors undergo minimal processing. This local differentiation ensures high reliability for problematic data while avoiding unnecessary power consumption on already-correct data, resolving the contradiction between error correction capability and circuit resource usage.
2Reliability
If code length is prolonged to handle burst errors, then error correction capability against burst errors is improved, but circuit scale and power consumption are increased
Solution Approach 1:
The data array is divided into multiple rows that can be processed independently through the two-stage error correction approach. This segmentation allows the system to handle burst errors that may affect multiple rows by treating each row separately in the second error correction stage, achieving robust burst error correction without requiring a single excessively long code that would increase circuit complexity.
Solution Approach 2:
The patent introduces a temporal dimension to error correction by implementing sequential processing across two stages. Rather than using a single long code in one dimension, the system distributes error correction across time (first processing, then second processing) and across multiple rows, effectively handling burst errors through dimensional distribution rather than code length extension.
Data Source
AI summary
An error correction circuit (20) according to this invention includes a first error correction processing circuit (21) configured to perform error correction processing in a row direction on array data having undergone first coding in the row direction, an error detection processing circuit (26) configured to perform error detection processing in a column direction on the array data having undergone second coding in the column direction, a corrected-bit likelihood calculation circuit (24) configured to calculate for each row the sum of likelihoods of corrected bits each of which is a bit corrected by the first error correction processing circuit (21), a high-likelihood row detection circuit (25) configured to detect rows of the array data in the descending order of the sums of likelihoods of corrected bits of respective rows output from the corrected-bit likelihood calculation circuit (24), and a second error correction processing circuit (27) configured to correct a bit at which a column error-detected by the error detection processing circuit (26) and a row detected by the high-likelihood row detection circuit (25) cross each other. An error correction circuit capable of improving transmission characteristics while suppressing the circuit scale can be provided.