LIN Bus Repeater Delay Compensation for Duty Cycle Integrity

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Solution Overview

Problem

The increasing complexity and cost of wiring in vehicles due to the disparate locations of sensors and components, coupled with propagation delays in local interconnected network (LIN) buses, lead to installation and maintenance challenges and communication unreliability.

Innovation Solution

An integrated circuit with measurement, control, and delay circuits that adjust bit times and edges to maintain a duty cycle, compensating for varying lengths and numbers of nodes in LIN buses, using digital counters and FET-based transmitters to regenerate data bits over longer distances.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If separate wiring is used to connect sensors and components at disparate locations to integrated circuits, then connectivity is achieved, but wiring complexity and installation cost increase

Engineering Contradiction:
ImproveconnectivityVSAvoidwiring complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

Multiple separate wiring connections are merged into a single LIN bus communication line. The patent implements a LIN bus network that allows multiple sensors and components to communicate with integrated circuits through a shared communication medium, eliminating the need for separate dedicated wires for each connection and significantly reducing wiring complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Physical wiring connections are replaced with electrical communication protocols. The patent uses LIN bus electrical signals to transmit data and control commands, substituting the mechanical act of connecting separate wires with an electrical field-based communication system that achieves the same connectivity function with reduced physical infrastructure.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Ease of operation

If LIN bus is used to reduce wiring complexity, then installation ease improves, but propagation delays cause communication unreliability

Engineering Contradiction:
Improveinstallation easeVSAvoidcommunication reliability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

Propagation delays are measured and compensated for in advance before actual communication occurs. The patent includes delay measurement circuits that determine the propagation delay characteristics of the LIN bus during initialization or calibration, then use these pre-measured values to adjust timing parameters for subsequent communications, ensuring reliable data transmission despite varying bus lengths.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system continuously monitors and adjusts for propagation delays using feedback mechanisms. The patent implements delay compensation circuits that receive feedback about actual signal propagation times and dynamically adjust timing parameters to maintain communication reliability, creating a closed-loop system that adapts to changes in bus configuration.

Inventive Principle:
Principle #23Feedback

3Adaptability or versatility

If LIN bus length varies to accommodate different node counts, then system flexibility improves, but duty cycle distortion occurs

Engineering Contradiction:
Improvesystem flexibilityVSAvoidduty cycle accuracy
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent dynamically changes timing parameters based on measured propagation delays. Delay compensation circuits adjust bit times, start-of-frame delays, and other timing parameters to compensate for variations in LIN bus length and node configuration, maintaining accurate duty cycles regardless of system flexibility requirements.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12562724B2Local interconnected network bus repeater delay compensation
Publication Date: 2026.02.24 AYDEEKAY LLC
  • US12562724B2 patent drawing
  • US12562724B2 patent drawing
  • US12562724B2 patent drawing

AI summary

An integrated circuit is described. This integrated circuit may include: a receive circuit, coupled to a segment of a LIN bus, that receives bits; a measurement circuit, coupled to the receive circuit, that measures: a rising-edge time and a falling-edge time in the bits, or a bit time and a second bit time in the bits; control logic, coupled to the measurement circuit, that compares the rising-edge time and the falling-edge time, or the bit time and the second bit time; a transmit circuit, coupled to the receive circuit, that transmits the bits on a second segment of the LIN bus; and a delay circuit, coupled to the control logic, that applies, based at least in part on the comparison, a delay to: one or more rising edges or falling edges in the bits; or one or more bit times or second bit times in the bits.