LIN Bus Transceiver Error Detection for Missing vs Incomplete Responses

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Solution Overview

Problem

Existing LIN bus systems struggle to distinguish between frame errors caused by a missing response and incomplete responses, complicating the circuitry of responder nodes and requiring complex buffer memory solutions.

Innovation Solution

Implementing a mechanism in LIN bus nodes to detect a flag indicating the presence of a recessive bit before a stop bit error, allowing differentiation between missing and incomplete responses through a simpler SR-latch or register-based approach.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If complex buffer memory solutions are used to distinguish between frame errors, then error detection accuracy is improved, but device complexity increases

Engineering Contradiction:
Improveerror detection accuracyVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts the essential error detection function from complex buffer memory solutions and implements it using a simple SR-latch that only needs to store a single bit indicating whether a recessive bit was detected. This extraction principle reduces the memory requirement from complex buffers to a minimal state machine, achieving accurate error differentiation without increasing circuit complexity

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The SR-latch automatically captures and stores the recessive bit detection state during the header reception phase, and this stored state is then used by the frame processor to differentiate error types. The system serves itself by using the detected state information without requiring external intervention or complex processing, thereby simplifying the overall circuit design while maintaining high error detection accuracy

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12547578B2LIN bus transceiver and method therefore
Publication Date: 2026.02.10 INFINEON TECHNOLOGIES AG
  • US12547578B2 patent drawing
  • US12547578B2 patent drawing
  • US12547578B2 patent drawing

AI summary

A method for a listening network node is described herein. In accordance with one embodiment, the method includes receiving data from a serial bus interface, wherein the data includes (at least) a first header of a first data frame. The method further includes detecting completion of the reception of the first header and detecting whether the data received subsequent to the first header includes a recessive bit and storing information that indicates whether or not a recessive bit has been detected. Furthermore, the method includes detecting a stop bit in the data received subsequent to the first header and, when the detection of the stop bit fails, detecting a break delimiter that indicates the end of a break field of a second header, signaling a frame error if the stored information indicates that a recessive bit has been received, and signaling a missing response if the stored information indicates that a recessive bit has not been received.