Negative Voltage Protection for LIN Bus Interface Devices

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Solution Overview

Problem

High voltage PMOS-based LIN bus interfaces face challenges with negative voltage protection, leading to parasitic PNP device turn-on and substrate noise, which affects slew rate control and increases noise in the LIN driver chip.

Innovation Solution

Incorporating a protective device between the power transistor and the LIN bus, controlled by a circuit that turns on when the bus voltage is above a certain level and turns off when it's at or below that level, to limit negative voltage excursions and prevent parasitic PNP device activation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If high voltage PMOS devices are used to replace bipolar transistors in LIN interfaces, then cost is reduced, but parasitic PNP device turn-on occurs and substrate noise increases

Engineering Contradiction:
ImprovecostVSAvoidsubstrate noise
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

An NPN transistor is introduced as an intermediary device between the PMOS power transistor and the LIN bus. The NPN transistor acts as a mediator that controls the timing of the PMOS transistor's operation, preventing parasitic PNP device turn-on while allowing the cost-effective PMOS device to be used. The NPN transistor's collector is connected to the PMOS gate, and its base is controlled by the control circuit to enable/disable the PMOS at appropriate times.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If high voltage diodes are used to protect PMOS devices from negative voltages, then negative voltage protection is provided, but parasitic PNP device turn-on is prevented and substrate noise increases

Engineering Contradiction:
Improvenegative voltage protectionVSAvoidsubstrate noise
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The NPN transistor serves as an intermediary that provides negative voltage protection without the harmful side effects of high voltage diodes. By controlling the NPN transistor's base through the control circuit, the PMOS transistor is enabled only when bus voltage is above the lower voltage level, providing protection while maintaining slew rate control and preventing parasitic turn-on.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The control circuit monitors the LIN bus voltage level and provides feedback control to the NPN transistor's base. When the bus voltage drops to or below the lower voltage level, the control circuit activates the NPN transistor to disable the PMOS power transistor, preventing parasitic PNP device turn-on. This feedback mechanism ensures protection while maintaining controlled slew rates.

Inventive Principle:
Principle #23Feedback

3Reliability

If the protective device is always on to protect from negative voltages, then negative voltage protection is ensured, but slew rate control is lost and parasitic PNP device turns on

Engineering Contradiction:
Improvenegative voltage protectionVSAvoidslew rate control
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The protective scheme transitions from a static always-on protective device to a dynamic controlled system. The NPN transistor's state is dynamically adjusted based on the LIN bus voltage level, being activated only when protection is needed (bus voltage at or below lower voltage level). This dynamic control maintains both protection and slew rate control capabilities.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The control circuit implements feedback control by monitoring the LIN bus voltage and adjusting the NPN transistor's state accordingly. When bus voltage is above the lower voltage level, the NPN remains off allowing normal PMOS operation and slew rate control. When bus voltage drops to or below the lower voltage level, the NPN turns on to provide protection, thus maintaining both protection and controlled slew rate.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11290108B2Negative voltage protection for bus interface devices
Publication Date: 2022.03.29 INFINEON TECHNOLOGIES AMERICAS CORP
  • US11290108B2 patent drawing
  • US11290108B2 patent drawing
  • US11290108B2 patent drawing

AI summary

A bus interface bus is described. A first logical state is conveyed over the bus by a higher voltage level and a second logical state is conveyed by a lower voltage level. An output stage of the interface includes a power transistor configured to drive the lower voltage level onto the bus to convey the second logical state, and a protective device between the power transistor and the bus. The protective device couples the power transistor to the bus when turned on and limits negative voltage excursions at the power transistor when turned off. A control circuit of the interface is configured to turn on the protective device when the bus voltage is above the lower voltage level and to turn off the protective device when the bus voltage is at or below the lower voltage level.