Line Based Thermal Image Processing Pipeline With Flexible Memory
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Solution Overview
Problem
Conventional frame-based image processing approaches in thermal imaging devices require significant processing power and memory resources, leading to processing delays and bottlenecks due to reliance on centralized memory systems and shared bus architectures.
Innovation Solution
Implementing line-based processing of thermal images, where individual lines of a thermal image frame are processed in stages of an image processing pipeline, and a flexible memory system is used to buffer and transfer data between components without relying on a single shared bus, allowing for simultaneous data transfers over different buses and asynchronous clock operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frame-based image processing is used, then complete image processing can be performed, but processing latency and bottlenecks increase due to centralized memory access
Solution Approach 1:
The patent divides the image processing task into line-based processing stages, where individual scan lines or small groups of lines are processed independently through pipeline stages rather than waiting for complete frame processing. This segmentation enables parallel processing of different line segments, reducing overall processing latency while maintaining complete image processing capability.
2Quantity of substance
If centralized memory system with shared bus is used, then data can be stored and accessed, but processing bottlenecks occur due to single bus contention
Solution Approach 1:
The patent transitions from a single shared bus architecture to a multi-dimensional bus system with multiple independent buses (first bus, second bus, third bus) that can operate simultaneously. This dimensional expansion of the data transfer pathway eliminates single bus contention bottlenecks while maintaining adequate memory capacity for storing processed line data.
3Loss of time
If line-based processing pipeline is implemented, then processing latency is reduced, but device complexity increases due to multiple buses and memory buffers
Solution Approach 1:
The patent designs the memory system with multi-functional components that can operate in different modes. The first memory buffer can store data for multiple pipeline stages, and the same buffer can serve different processing functions at different times. This universality reduces the need for separate dedicated memory structures for each pipeline stage, thereby reducing overall device complexity while maintaining low processing latency.
4Productivity
If multiple components transfer data simultaneously, then processing efficiency improves, but bus conflicts occur without proper arbitration
Solution Approach 1:
The patent introduces a bus arbitration mechanism that acts as an intermediary between multiple data transfer requests and the available bus resources. The arbiter selectively grants bus access to different components based on priority and timing, enabling simultaneous data transfers across multiple buses while preventing conflicts and ensuring reliable data transfer.
Data Source
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AI summary
Techniques are provided to implement line based processing of thermal images and a flexible memory system. In one example, individual lines of a thermal image frame may be provided to an image processing pipeline. Image processing operations may be performed on the individual lines in stages of the image processing pipeline. A memory system may be used to buffer the individual lines in the pipeline stages. In another example, a memory system may be used to send and receive data between various components without relying on a single shared bus. Data transfers may be performed between different components and different memories of the memory system using a switch fabric to route data over different buses. In another example, a memory system may support data transfers using different clocks of various components, without requiring the components and the memory system to all be synchronized to the same clock source.