Line Buffer Controller for Image Processing Cycle Smoothing
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Solution Overview
Problem
Image processing apparatuses face inefficiencies due to fixed transmission rates of pixel data, leading to varying processing times per line, which can result in excessive computing requirements and idle time, especially when dealing with distortion corrections in images from capture devices like cameras with super-wide-angle lenses.
Innovation Solution
The implementation of multiple line buffers and a controller that synchronizes the writing and reading of pixel data with horizontal synchronization signals, allowing for the smoothing of processing cycles across multiple periods and reducing the necessary computing speed by aligning write and read operations with the completion of image processing on each line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the operation frequency or computing unit is designed based on the maximum number of peak cycles necessary to process pixel data in real time, then the image processing can keep up with the fixed transmission rate of pixel data, but the computing unit operates at excessively high speed for most lines, resulting in idle time and reduced productivity
Solution Approach 1:
The patent applies dynamics by making the line buffer capacity variable rather than fixed. The controller dynamically adjusts the number of lines stored in the line buffer based on the actual processing time required for each line. This allows the system to adapt to varying processing demands of different lines, ensuring real-time processing capability is maintained only when necessary, while improving overall processing efficiency by reducing idle time for lines that require less processing.
2Reliability
If pixel data is written in the line buffer in real time at a fixed rate, then the data transmission is simplified and reliable, but the processing time varies for each line causing idle time in the computing unit
Solution Approach 1:
The patent applies preliminary action by pre-writing pixel data into the line buffer at a fixed reliable rate before processing begins. The controller determines the required buffer capacity in advance based on processing time measurements, and pre-allocates the appropriate number of lines in the buffer. This ensures data transmission stability is maintained while preventing idle time by having the exact amount of data needed ready before processing starts.
3Device complexity
If a single line buffer is used to store pixel data for processing, then the device complexity is reduced, but the line buffer capacity must be large enough to handle the maximum processing requirements, increasing manufacturing costs
Solution Approach 1:
The patent applies dynamics by implementing a controllable line buffer whose capacity can be dynamically adjusted by the controller. Instead of using a fixed large buffer to handle maximum requirements, the system dynamically allocates buffer space based on actual processing needs. This maintains device simplicity with a single buffer structure while reducing manufacturing costs by minimizing the required buffer capacity to only what is necessary for real-time processing.
Data Source
AI summary
An image processing apparatus includes first and second line buffers, an image processing circuit configured to perform an image processing on first pixel data stored in the first line buffer and then second pixel data stored in the second line buffer, and a controller configured to control writing of the second pixel data in the second line buffer at a timing aligned with a synchronizing signal and reading of the second pixel data written in the second line buffer for the image processing by the image processing circuit at a timing of a completion of the image processing by the image processing circuit of the first pixel data stored in the first line buffer.