Line Buffer Power Reduction via Data Skip Logic
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Solution Overview
Problem
Conventional image processing apparatuses with line buffers face limitations in reducing power consumption, as clock gating methods alone are insufficient to achieve significant energy savings.
Innovation Solution
The proposed image processing apparatus includes a line buffer, a clock gating circuit, and a data processor that determines whether to skip write or read operations based on adjacent data values. The data processor controls the clock gating circuit to conserve power by preventing clock signal application during skipped operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock gating method is used to reduce power consumption, then power consumption is reduced, but power consumption reduction is limited and insufficient
Solution Approach 1:
The patent applies the skipping principle by detecting adjacent identical data in the image buffer and skipping redundant write operations for these identical data. When adjacent data values are the same, the system skips the write operation and clock signal application, thereby significantly reducing power consumption beyond what traditional clock gating alone can achieve. This is implemented through a data processor that compares adjacent data values and generates skip signals to prevent unnecessary operations.
2Reliability
If write operation is performed for all adjacent data, then data integrity is maintained, but power consumption increases due to unnecessary operations
Solution Approach 1:
The patent implements feedback by continuously monitoring and comparing adjacent data values in the image buffer. The data processor provides feedback signals based on whether adjacent data values are identical, which then control subsequent write operations and clock signal application. This feedback mechanism ensures that write operations are performed only when necessary (when data values differ), maintaining data integrity while reducing power consumption by eliminating redundant operations.
3Reliability
If clock signal is continuously applied to line buffer, then operation reliability is ensured, but power consumption increases due to unnecessary clock applications
Solution Approach 1:
The patent applies periodic action by controlling the clock signal to be applied only periodically when necessary, rather than continuously. The clock gating circuit receives control signals from the data processor that determine when the clock signal should be applied to the line buffer. When adjacent identical data is detected, the clock signal is gated off, creating a periodic or event-driven clock application pattern that maintains operation reliability only when needed while significantly reducing power consumption during redundant operations.
Data Source
AI summary
An image processing apparatus includes: a line buffer configured to store image data; a clock gating circuit configured to apply a clock signal to the line buffer; and a data processor configured to determine, when performing a write operation, whether to skip the write operation to the line buffer for each of adjacent data according to whether a value of each of the adjacent data within an image is the same, wherein the data processor is further configured to control the clock gating circuit, such that the clock signal is prevented from being applied to the line buffer while the write operation is skipped and the clock signal is applied to the line buffer while the write operation is performed.