Line Card SYSCLK Generation Without PLL Backplane Distribution
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Solution Overview
Problem
In network communication systems, distributing the SYSCLK clock signal from a master timing card to all line cards over a backplane is inefficient and prone to misalignment due to variations in process, voltage, and temperature, which affects the synchronization of time of day counters across different line cards.
Innovation Solution
Generating the SYSCLK signal using a digitally controlled oscillator on each line card, which receives a timing signal from the SyncE phase-locked loop and a control signal from control logic, eliminating the need for backplane distribution and allowing for phase and frequency alignment with the SYNC signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the SYSCLK clock signal is distributed from the master timing card to all line cards over the backplane, then the clock signal can be provided to all line cards, but signal misalignment occurs due to PVT variations and routing differences
Solution Approach 1:
The system divides the clock generation function into segments: the master timing card generates the SyncE reference clock and distributes it to line cards, while each line card independently generates its own SYSCLK using a locally controlled oscillator. This segmentation eliminates the need to distribute SYSCLK over the backplane and removes PVT-related misalignment issues.
Solution Approach 2:
The control logic on each line card uses feedback from the locally generated SYNC signal to adjust the frequency and phase of the locally generated SYSCLK. This closed-loop feedback mechanism ensures that the locally generated clock remains synchronized with the network timing without requiring physical distribution of the clock signal.
2Ease of operation
If the SYSCLK is distributed over the backplane, then all line cards receive the clock signal, but the routing and pin requirements increase
Solution Approach 1:
The invention extracts the SYSCLK generation function from the master timing card and relocates it to individual line cards. Each line card now generates its own SYSCLK locally using a controlled oscillator, eliminating the need for backplane distribution of this signal and reducing pin requirements.
Solution Approach 2:
Each line card serves itself by generating its own SYSCLK signal through a locally implemented controlled oscillator that is adjusted by control logic based on locally generated SYNC signals. This self-service approach eliminates dependence on the master timing card for SYSCLK distribution.
3Manufacturing precision
If a PLL is used on each line card to generate SYSCLK, then frequency and phase alignment can be achieved, but device complexity increases
Solution Approach 1:
The invention changes the fundamental parameter of clock generation by replacing the PLL architecture with a controlled oscillator architecture. The controlled oscillator's frequency and phase are directly adjusted by control logic based on SYNC signal timing, achieving the same alignment goal with simpler circuitry.
Data Source
AI summary
A line card in a network box receives a SyncE clock signal and an input synchronization (SYNC) signal. A phase-lock loop (PLL) in the line card receives the SyncE clock signal as a reference clock signal and generates an output SyncE clock signal. The line card regenerates a SYSCLK signal using a digitally controlled oscillator that receives a timing signal from the SyncE PLL and receives a control signal from control logic on the line card. The frequency and phase information contained in the SYNC signal is utilized to control the DCO. The SYSCLK signal is divided to generate an output SYNC signal. The control logic uses the time difference between the input SYNC signal and a SYNC feedback signal to control the DCO to provide a zero delay SYNC output signal. The output SYNC signal and the SYSCLK signal control a time of day counter in the line card.