Line Card SYSCLK Regeneration Without Backplane Clock Distribution
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Solution Overview
Problem
In network communication systems, distributing the SYSCLK clock signal from a master timing card to all line cards over a backplane can lead to misalignment and increased complexity due to variations in process, voltage, and temperature, as well as requiring additional routing and pins.
Innovation Solution
Generating the SYSCLK clock signal on each line card using a digitally controlled oscillator (DCO) that receives a timing signal from the SyncE phase-locked loop and a control signal from control logic, eliminating the need for the master timing card to distribute SYSCLK, and using a divider circuit to synchronize the time of day counters with the SYNC output signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the SYSCLK clock signal is distributed from the master timing card to all line cards over the backplane, then all line cards can receive a centralized clock signal, but this increases backplane routing complexity and pin requirements while causing misalignment due to PVT variations
Solution Approach 1:
The patent divides the centralized clock distribution system into multiple independent segments. Each line card generates its own SYSCLK locally using a digitally controlled oscillator instead of receiving it from the master timing card. This segmentation eliminates the need for extensive backplane routing while ensuring each segment (line card) has an independent, aligned clock source that is synchronized through the SYNC signal rather than shared SYSCLK distribution.
2Reliability
If the SYSCLK clock signal is distributed from the master timing card to all line cards over the backplane, then all line cards can receive a centralized clock signal, but this increases pin requirements on the backplane
Solution Approach 1:
The patent extracts the SYSCLK generation function from the master timing card and relocates it to each individual line card. By taking out the clock generation capability from the centralized master card and placing it in each slave line card, the system eliminates the need for multiple backplane pins dedicated to SYSCLK distribution, while maintaining reliable clock signal generation through local DCOs controlled by SYNC timing.
3Device complexity
If a digitally controlled oscillator generates SYSCLK locally on each line card, then backplane routing is reduced and pin requirements are minimized, but synchronization accuracy must be maintained across PVT variations
Solution Approach 1:
The patent implements a feedback mechanism where the locally generated SYSCLK on each line card is controlled by a digitally controlled oscillator that receives timing control from the SYNC signal. The DCO adjusts its output frequency and phase based on feedback from the SYNC signal timing, ensuring that even though each line card generates its own clock, the synchronization accuracy is maintained across PVT variations through closed-loop control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the need for backplane routing, minimizes pin requirements, and ensures accurate synchronization of time of day counters across line cards by regenerating the SYSCLK signal locally, maintaining alignment despite PVT variations and eliminating IO delay.
Implementation Method 1
generating a first output clock signal using a phase-locked loop and supplying a clock signal from the phase-locked loop to a digitally controlled oscillator
Implementation Method 2
generating a second output clock signal using the digitally controlled oscillator
Implementation Method 3
dividing the second output clock signal to generate a SYNC output signal
Data Source
AI summary
A line card in a network box receives a SyncE clock signal and an input SYNC signal. A phase-lock loop (PLL) in the line card receives the SyncE clock signal as a reference clock signal and generates an output SyncE clock signal. The line card regenerates a SYSCLK signal using a digitally controlled oscillator that receives a timing signal from the SyncE PLL and receives a control signal from control logic on the line card. The frequency and phase information contained in the SYNC signal is utilized to control the DCO. The SYSCLK signal is divided to generate an output SYNC signal. The control logic uses the time difference between the input SYNC signal and a SYNC feedback signal to control the DCO to provide a zero delay SYNC output signal. The output SYNC signal and the SYSCLK signal control a time of day counter in the line card.