Line-Coupled Clock Circuit Using FLL and Staggered Counters
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Solution Overview
Problem
Existing methods for generating line-coupled clocks in digital ICs require precise phase measurement, which is resource-intensive and prone to interference, especially when dealing with digital synchronization signals, and often necessitate analog filters and AD converters, complicating the process.
Innovation Solution
A method and circuit using a Frequency Locked Loop (FLL) with staggered counters to generate a line-coupled clock, eliminating the need for phase measurement by regulating the clock's frequency relative to a synchronization signal, allowing for precise clock generation using a purely digital design without the need for AD converters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If phase measurement is performed using a digital PLL with analog filters and AD converters, then phase precision is improved, but device complexity and susceptibility to interference increase
Solution Approach 1:
The patent replaces the mechanical/analog signal processing system (analog filters, AD converters, clamping circuits) with a purely digital counting system. The phase measurement function is substituted by digitally counting clock cycles between synchronization edges, eliminating the need for analog-to-digital conversion and complex analog filtering while maintaining measurement precision.
Solution Approach 2:
The patent extracts and eliminates the unnecessary analog components (filters, AD converters, clamping circuits) from the phase measurement system. By taking out these complex analog elements and replacing them with simple digital counters, the system achieves the same measurement function with reduced complexity and improved interference resistance.
2Measurement precision
If analog filters and AD converters are used for phase measurement, then phase precision is improved, but susceptibility to interference and measurement errors increases
Solution Approach 1:
The patent substitutes the analog measurement chain with a digital counting approach. By using digital counters to measure the number of clock cycles between synchronization edges, the system eliminates analog filters and AD converters that are susceptible to interference, noise, and distortion. The digital domain inherently provides immunity to these harmful factors.
Solution Approach 2:
The patent replaces expensive and complex analog components (high-precision AD converters, analog filters, clamping circuits) with simple, robust digital counters. The digital counting method uses basic digital logic elements that are less susceptible to interference and do not require precise analog signal conditioning, thereby reducing vulnerability to harmful factors.
3Measurement precision
If phase measurement is performed with digital PLL, then phase precision is improved, but the requirement for additional digital hardware increases
Solution Approach 1:
The patent replaces the complex digital PLL phase measurement architecture with a simpler digital counting system. Instead of using phase detectors, charge pump circuits, and multiple digital components, the invention uses basic digital counters to measure clock cycles, significantly reducing the quantity of digital hardware required while maintaining measurement precision.
4Measurement precision
If external processing of analog synchronization impulses is performed, then phase measurement capability is improved, but precision is lost or additional digital circuits are required
Solution Approach 1:
The patent inverts the conventional approach by not externally processing analog synchronization impulses through complex circuits. Instead, it uses a simple digital counter to directly measure the number of clock cycles between synchronization edges, achieving phase measurement capability without external analog processing or additional complex digital circuits.
Data Source
AI summary
The invention relates to a method or to a correspondingly equipped circuit for line-coupled generation of a clock (t), wherein the clock (t) is controlled in relation to a synchronization signal (hs) and by means of a closed loop (FLL) with respect to the phase and/or the frequency in relation to the synchronization signal (hs); wherein a plurality (n) of at least two count values (cn, c0-c7) is determined, wherein each of the count values (cn, c0-c7) is determined with at least one count duration number (z) of consecutive periods of the synchronization signal (hs), and wherein each of the count values (cn, c0-c7) is determined offset relative to at least one further count value (cn, c0-c7) with a count offset (v) which is different from the count duration number of consecutive periods of the synchronization signal (hs).