Line Defect Detection Circuit Using Dual-End Stress Drivers
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Solution Overview
Problem
As semiconductor devices become more highly integrated, detecting defects in lines on patterned memories, such as memory cell arrays, is challenging due to the decreasing widths of lines and intervals, leading to potential failures during manufacturing and usage, which existing burn-in tests may not effectively identify early enough.
Innovation Solution
A line defect detection circuit is introduced, featuring first and second drivers at each end of the lines, utilizing PMOS and NMOS transistors to apply control and stress signals, respectively, to increase the stress effect on lines during a burn-in test, allowing for early detection of weak lines and defects in contacts or via holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional burn-in tests are used to detect line defects, then device reliability is improved, but weak line defects cannot be detected early enough due to insufficient stress application
Solution Approach 1:
The patent changes the electrical parameters (voltage levels and current magnitude) applied to the line during testing. By using higher voltage levels and increased current magnitude than traditional burn-in tests, the patent enhances the stress effect on weak lines, enabling early detection of defects that would not be detected under normal operating conditions or standard burn-in protocols.
Solution Approach 2:
The patent applies excessive stress to the line by driving it with high current for a short duration. This excessive action temporarily exceeds normal operating conditions to provoke a response from weak lines, causing them to fail or exhibit detectable anomalies that would not appear under normal conditions, thereby enabling early defect identification.
2Productivity
If line width and interval are decreased for high integration, then device functionality is improved, but line defect detection becomes more difficult
Solution Approach 1:
The patent changes the electrical parameters applied to the line, using higher voltage and current magnitude to compensate for the reduced line dimensions. This enhanced parameter application creates sufficient stress effect on narrow, closely-spaced lines to reveal defects that would be difficult to detect with traditional testing methods.
Solution Approach 2:
The patent performs preliminary stress testing on lines before final device operation. By applying high stress early in the testing process, weak lines are provoked to fail or exhibit detectable anomalies before the device is deployed, enabling early defect identification in highly integrated structures where defects are particularly difficult to detect.
3Measurement precision
If high current is applied for short period to detect weak lines, then detection capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the detection process into distinct phases: a normal operation mode and a stress application mode. The stress mode is activated only when needed for defect detection, using control signals to selectively enable high current application. This segmentation allows the circuit to maintain simplicity during normal operation while providing enhanced detection capability when required.
Solution Approach 2:
The patent implements dynamic switching between different operational states. The detection circuit can dynamically transition from normal low-power operation to high-stress testing mode and back again, controlled by external signals. This dynamic behavior allows the same circuit structure to serve multiple functions without requiring separate dedicated hardware for each mode, thereby limiting the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The line defect detection circuit effectively identifies weak lines and defects by applying a strong current for a short period, enhancing the reliability of semiconductor devices by detecting issues before they cause failures, thereby reducing the likelihood of initial, accidental, and wear-out failures.
Implementation Method 1
a first driver disposed at one end of a line and configured to drive the line using a first voltage or a second voltage in response to a control signal
Implementation Method 2
a second driver disposed at the other end of the line and configured to drive the line using the second voltage in response to a stress signal
Implementation Method 3
The line defect detection circuit effectively identifies weak lines and defects by applying a strong current for a short period
Data Source
AI summary
Example embodiments relate to a line defect detection circuit, including a first driver disposed at one end of a line and configured to drive the line using a first voltage or a second voltage in response to a control signal, and a second driver disposed at the other end of the line and configured to drive the line using the second voltage in response to a stress signal.