Line Driver Pre-Driver Split for Feed-Through Capacitance Loading

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

High-speed SerDes interfaces are limited by inter-signal interference (ISI) due to heavy loading at the line driver output, including self-capacitance, ESD capacitance, package capacitance, and PCB trace capacitance, which restricts bandwidth and data rate.

Innovation Solution

A line driver with separate pre-drivers for differential pair transistors and feed-through capacitance, allowing independent optimization and timing control to reduce loading effects, utilizing a timing-controlled cascade feed-through technique to manage the feed-through capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single pre-driver is used to drive both the differential pair and feed-through capacitance, then the device complexity is reduced, but the line driver becomes bandwidth limited due to heavy loading

Engineering Contradiction:
Improvepre-driver structureVSAvoidbandwidth
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The patent divides the single pre-driver into two separate pre-drivers: one dedicated to driving the differential pair transistors and another dedicated to driving the feed-through capacitance. This segmentation allows each pre-driver to be optimized independently, reducing the overall loading effect and increasing the bandwidth of the line driver without significantly increasing device complexity.

Inventive Principle:
Principle #1Segmentation

2Speed

If separate pre-drivers are used for differential pair and feed-through capacitance, then the bandwidth is increased, but the device complexity increases

Engineering Contradiction:
ImprovebandwidthVSAvoidpre-driver structure
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

While using separate pre-drivers, the patent merges their outputs to drive the respective components (differential pair and feed-through capacitance) in a coordinated manner. The timing-controlled cascade configuration merges the signal paths to achieve complementary effects that reduce overall loading and enhance bandwidth.

Inventive Principle:
Principle #5Merging (Combining)

3Speed

If feed-through capacitance is used to reduce rise/fall time, then the speed is improved, but the loading on the line driver increases

Engineering Contradiction:
Improverise/fall timeVSAvoidloading effect
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a dedicated second pre-driver as an intermediary between the control signal and the feed-through capacitance. This intermediary specifically manages the charging/discharging of the feed-through capacitance, allowing it to reduce rise/fall time while the first pre-driver manages the differential pair without bearing the full loading burden.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9344081B2Line driver with separate pre-driver for feed-through capacitance
Publication Date: 2016.05.17 LATTICE SEMICON CORP
  • US9344081B2 patent drawing
  • US9344081B2 patent drawing
  • US9344081B2 patent drawing

AI summary

Embodiments of the invention are generally directed to a line driver with separate pre-driver for feed-through capacitance. An embodiment of an apparatus includes a differential pair of transistors to generate an output signal on a first output node and a second output node; a pass-through capacitance coupled with the first output node and the second output node; a first pre-driver to drive an input signal for the differential transistors; and a second pre-driver to drive the input signal for the pass-through capacitance.