Line Driver Circuits Reducing GIDL via Dynamic Voltage
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Solution Overview
Problem
Conventional memory array line drivers experience increased gate-induced diode leakage (GIDL) and device stress during inactive periods due to the connection of inactive word lines to negative voltage, which reduces sub-threshold leakage but causes undesirable GIDL and stress on transistors.
Innovation Solution
The line driver is configured to provide a ground or positive-level pull-down voltage to the gate of transistors during inactive periods, reducing the voltage differential across transistors and minimizing GIDL and device stress, while maintaining reduced sub-threshold leakage during active periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If inactive word lines are connected to negative voltage during inactive periods, then sub-threshold leakage is reduced, but gate-induced diode leakage (GIDL) and device stress increase
Solution Approach 1:
The patent implements dynamic voltage adjustment by switching between negative voltage and ground/positive-level voltage based on the operational state (active vs. inactive) of the memory array. During inactive periods, the voltage on inactive word lines is dynamically changed from negative to ground/positive level, reducing GIDL while maintaining low sub-threshold leakage through controlled voltage transitions.
Solution Approach 2:
The patent changes the voltage parameter from a fixed negative voltage to a variable voltage that can be switched between negative voltage (during active periods) and ground/positive-level voltage (during inactive periods). This parameter change resolves the contradiction by adapting the voltage level to the operational requirements, minimizing both sub-threshold leakage and GIDL.
2Loss of energy
If negative voltage is applied to control lines during inactive mode, then sub-threshold leakage across memory cells is reduced, but transistor stress increases
Solution Approach 1:
The patent applies dynamic voltage switching to the control lines, transitioning from static negative voltage to dynamic voltage adjustment. During inactive mode, the voltage is switched from negative to ground/positive level, dynamically reducing transistor stress while maintaining low sub-threshold leakage through timing-controlled voltage transitions.
Solution Approach 2:
The voltage parameter on control lines is changed from a constant negative value to a variable parameter that adapts to operational mode. This parameter change reduces transistor stress by eliminating the large voltage differential during inactive periods while preserving the leakage reduction benefit during active periods.
Data Source
AI summary
Described embodiments are directed to line drivers, such as those for providing reduced gate induced drain leakage in a memory array. Corresponding methods of operation of line drivers are also disclosed.