Line Driver Circuit Using Level Conversion for Over-Voltage Protection

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Solution Overview

Problem

Existing line driver circuits are vulnerable to high voltages, which can exceed the breakdown voltage of PMOS and NMOS transistors, leading to transistor degradation and failure over time.

Innovation Solution

The proposed line driver circuit incorporates a multitude of PMOS and NMOS transistors that receive level-converted voltages and reference voltages, ensuring that the gate-to-source and gate-to-drain voltages of the transistors remain below their respective junction breakdown voltages, even at high supply voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the supply voltage is increased to drive the load over long distances, then the driving capability is improved, but the junction voltage of PMOS and NMOS transistors exceeds their breakdown voltage, leading to transistor degradation and failure

Engineering Contradiction:
Improvedriving capabilityVSAvoidtransistor reliability
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The patent introduces intermediary voltage level converters between the high-voltage supply and the transistor gates. These converters mediate the voltage transmission by converting the high supply voltage into appropriate gate drive voltages that keep transistor junction voltages below breakdown levels, thus protecting transistors while maintaining high-voltage driving capability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the voltage parameters through multiple stages: it converts the high supply voltage (3.63V) into intermediate voltage levels using voltage level converters, ensuring that gate-to-source and gate-to-drain voltages remain within safe operating ranges. This parameter transformation allows the circuit to operate at high supply voltages without exceeding transistor breakdown voltages

Inventive Principle:
Principle #35Parameter changes

2Reliability

If level-converted voltages are applied to keep junction voltages below breakdown voltage, then transistor protection is improved, but the circuit complexity increases due to multiple voltage level converters and reference voltage circuits

Engineering Contradiction:
Improvetransistor protectionVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple voltage level conversion functions into a coordinated system where the first, second, and third voltage level converters work together with the reference voltage circuits. By combining these functions and sharing common reference voltages (first reference voltage and second reference voltage), the circuit achieves comprehensive transistor protection while managing complexity through functional integration

Inventive Principle:
Principle #5Merging (Combining)

3Manufacturing precision

If multiple voltage level converters and reference voltage circuits are used, then voltage control precision is improved, but the manufacturing complexity and cost increase

Engineering Contradiction:
Improvevoltage control precisionVSAvoidmanufacturing ease
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent implements universal reference voltage circuits that serve multiple purposes: the first reference voltage is used by both the second voltage level converter and the second PMOS transistor, while the second reference voltage is used by both the third voltage level converter and the third PMOS transistor. This multi-functionality reduces the total number of independent voltage generation circuits, simplifying manufacturing while maintaining precise voltage control

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12218662B1Line driver with high over-voltage protection
Publication Date: 2025.02.04 SYNOPSYS INC
  • US12218662B1 patent drawing
  • US12218662B1 patent drawing
  • US12218662B1 patent drawing

AI summary

A line driver circuit include a multitude of PMOS and NMOS transistors. A first PMOS transistor receives an output voltage of a first level converter. A second PMOS transistor receives a first reference voltage. A third and fourth PMOS transistors receive an output voltage of a second voltage level converter. The source terminal of the first PMOS transistor receives the supply voltage. The drain terminal of the fourth PMOS transistor is coupled to an output terminal of the line driver circuit. A first NMOS transistor receives an input signal. A second NMOS transistor receives a second reference voltage. A third and fourth NMOS transistors receive an output voltage of a third level converter. The first NMOS transistor receives a ground potential. The drain terminal of the fourth NMOS transistor is coupled to the output terminal of the line driver. The first, second and third voltage converters receive the input signal.