Line-End Hole Classification in IC Layout Design
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Solution Overview
Problem
Current integrated circuit layout design methods fail to efficiently distinguish and treat single and redundant line-end holes, leading to increased repair and review rates, as well as higher design and mask tape out costs.
Innovation Solution
A method that selects line-end hole features from integrated circuit layouts, classifies them into single and redundant hole features based on spacings between adjacent holes, allowing for individual repair of single holes while omitting redundant holes, without requiring layout design information from other layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all line-end holes are treated uniformly without classification, then the design process is simple, but repair and review rates increase due to inability to distinguish single holes from redundant holes
Solution Approach 1:
The patent segments the hole feature into two distinct categories: single hole feature and redundant hole feature, based on spacing measurements between adjacent holes. This segmentation allows differential treatment where single holes receive repair attention while redundant holes are omitted, thereby reducing repair and review rates without requiring complex multi-layer analysis
Solution Approach 2:
The classification method uses the hole feature's own spacing characteristics to automatically distinguish between single and redundant holes. The system self-identifies which holes need repair based on their spatial relationships, eliminating the need for external layout information from other layers and enabling autonomous decision-making in the repair process
2Measurement precision
If layout design information from multiple layers is used for hole classification, then classification accuracy improves, but mask tape out time and design costs increase
Solution Approach 1:
The patent extracts only the necessary spacing information from the hole feature itself, removing the dependency on layout design information from other layers. By taking out only the essential spacing parameter needed for classification, the method achieves accurate differentiation between single and redundant holes while significantly reducing mask tape out time and design costs
3Reliability
If all holes are repaired individually, then repair completeness is high, but treatment time and costs increase
Solution Approach 1:
The patent applies local quality by treating different types of holes differently based on their classification. Single holes receive individual repair treatment to ensure repair completeness, while redundant holes are systematically omitted to improve treatment efficiency. This localized differential treatment optimizes both reliability and productivity by matching the treatment intensity to the actual need of each hole type
Data Source
AI summary
A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.