Line-End Shrinking Lithography Using Sidewall Spacers
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Solution Overview
Problem
Existing lithographic techniques face challenges in achieving precise alignment and feature separation due to complex interactions and strict design rules, limiting the ability to manufacture smaller, more robust circuit devices.
Innovation Solution
The use of a line-end shrinking technique that eliminates the need for a separate line-cut exposure by forming a spacer on the sidewalls of the resist layer, allowing for the separation of features without additional patterning steps and relaxing design rules, enabling the formation of smaller features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple lithographic patterning iterations are performed to define smaller critical dimensions, then manufacturing precision is improved, but device complexity and process complexity increase
Solution Approach 1:
The patent applies preliminary action by forming spacers on the sidewalls of the resist layer before the line-cut exposure step. This pre-positioning of features through spacer formation allows the subsequent line-cut to proceed more effectively, reducing the need for multiple iterative patterning steps and simplifying the overall process while achieving the desired small critical dimensions
Solution Approach 2:
The patent uses spacers as intermediary structures formed on the sidewalls of the resist layer. These spacers serve as mediators that define feature positions and enable precise pattern transfer without requiring complex multiple patterning iterations, thereby reducing process complexity while maintaining manufacturing precision
2Manufacturing precision
If strict design rules are followed for lithographic techniques, then manufacturing precision is maintained, but adaptability and design flexibility are reduced
Solution Approach 1:
The patent employs self-service through self-aligned spacer formation where the spacers are automatically positioned on the sidewalls of the resist layer based on the resist pattern itself. This self-alignment mechanism eliminates the need for strict external design rules and complex alignment procedures, providing design flexibility while maintaining manufacturing precision
Solution Approach 2:
The patent utilizes parameter changes in the spacer formation process, where the spacer width and position are controlled by deposition parameters rather than strict lithographic design rules. This allows greater adaptability in feature design while maintaining the precision needed for pattern transfer
3Manufacturing precision
If additional patterning steps are performed for feature separation, then manufacturing precision is improved, but productivity and manufacturing efficiency decrease
Solution Approach 1:
The patent merges the feature separation function into the spacer formation step itself. The spacers formed on the sidewalls inherently provide feature separation without requiring a separate additional patterning step, thereby maintaining manufacturing precision while improving productivity and manufacturing efficiency
Data Source
AI summary
A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a dataset specifying a plurality features to be formed on the workpiece. A first patterning of a hard mask of the workpiece is performed based on a first set of features of the plurality of features, and a first spacer material is deposited on a sidewall of the patterned hard mask. A second patterning is performed based on a second set of features, and a second spacer material is deposited on a sidewall of the first spacer material. A third patterning is performed based on a third set of features. A portion of the workpiece is selectively processed using a pattern defined by a remainder of at least one of the patterned hard mask layer, the first spacer material, or the second spacer material.