Line Interleaving Controller Virtual Data Lines TDM
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing image signal processors face increased power consumption and size/cost due to external frame memory usage in time-division multiplexing (TDM) schemes, and interference between channels during image processing.
Innovation Solution
A line interleaving controller generates virtual data lines to support efficient TDM by units of lines, reducing channel interference and minimizing external memory access, integrated with an image signal processor core that includes a pipeline circuit for sequential processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an external frame memory is used for TDM processing, then the image signal processor can store and process multiple input images, but power consumption increases due to bus transactions
Solution Approach 1:
The frame memory is merged with the image signal processor to form an integrated structure, eliminating the need for external bus transactions. The memory controller within the processor directly manages data flow between the frame memory and processing units, reducing power consumption while maintaining TDM capability
Solution Approach 2:
A memory controller acts as an intermediary between the frame memory and processing units, managing data flow efficiently. This intermediary enables the processor to access frame data without direct bus transactions, reducing power consumption while maintaining full TDM processing capability
2Adaptability or versatility
If an external frame memory is used for TDM processing, then the image signal processor can handle multiple channels, but device size and cost increase
Solution Approach 1:
The frame memory is integrated within the image signal processor rather than being external, reducing overall device size. The memory shares the processor's physical space and is managed by an internal memory controller, eliminating the need for separate external memory components
Solution Approach 2:
The integrated frame memory serves multiple functions: storing data from multiple channels, providing data to parallel processing units, and supporting TDM operations. This multi-functional design reduces the need for separate memory components for different processing tasks
3Use of energy by moving object
If frame memory is included in the image signal processor, then power consumption is reduced, but the size of the image signal processor increases
Solution Approach 1:
The image signal processor is segmented into functional units including the memory controller, processing units, and frame memory. This segmentation allows efficient local data access within the processor, reducing power consumption while the overall layout optimizes space utilization
4Reliability
If TDM processing is implemented without virtual data lines, then channel interference occurs during end image data line processing, but adding virtual data lines increases processing complexity
Solution Approach 1:
Virtual data lines act as intermediaries between the buffer circuit and processing units, preventing direct channel interference during end image data line processing. These virtual lines buffer and manage data flow, eliminating interference while the memory controller automates the process to minimize added complexity
Data Source
AI summary
An image signal processor includes a line interleaving controller and an image signal processor core. The line interleaving controller receives a plurality of image data lines included in an image frame, generates one or more virtual data lines corresponding to the image frame, and outputs the plurality of image data lines and the virtual data lines sequentially line by line. The image signal processor core includes at least one pipeline circuit. The pipe line circuit includes a plurality of processing modules serially connected to sequentially process data lines received from the line interleaving controller. The line interleaving controller processes one or more end image data lines included in an end portion of the image frame based on the virtual data lines. Interference or collision between channels is reduced or prevented by processing the end image data lines in synchronization with the virtual data lines.