Line-Shaped Mask SAC Technique for DRAM Sense Amplifier Downscaling
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Solution Overview
Problem
The SAC hole technique used for forming contact plugs in ring-gate transistors results in a long distance between the contact plug and the gate electrode, hindering downscaling of DRAM and other circuits due to the time required for etchant to move through narrow holes and the need for a thick gate gap and sidewall to prevent damage, which enlarges the transistor size and limits chip size reduction.
Innovation Solution
A manufacturing method using a line-shaped opening in a mask layer to selectively remove the insulation layer and form contact plugs, allowing the etchant to move efficiently and reducing the distance between the contact plug and the gate electrode, employing a line SAC technique to form contact plugs connected to source and drain regions of transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the SAC hole technique is used to form contact plugs, then the contact plugs are formed in self-alignment, but the distance between contact plug and gate electrode becomes long
Solution Approach 1:
The patent changes the mask opening shape from point-like (SAC hole) to line-shaped, utilizing a different geometric dimension. This line-shaped opening allows etchant to access multiple contact holes simultaneously through the line structure, reducing the required gate gap thickness and thus the distance between contact plug and gate electrode while maintaining self-alignment
2Reliability
If the gate gap and sidewall thickness are increased to prevent gate electrode damage, then the gate electrode is protected, but the transistor size is enlarged
Solution Approach 1:
The patent changes the geometric parameters of the mask opening from small circular holes to extended line shapes. This parameter change allows the same protective function to be achieved with smaller gate gap thickness, thereby reducing transistor area while maintaining gate electrode protection during the etching process
3Manufacturing precision
If narrow contact holes are used for precise contact formation, then the contact alignment is precise, but the etching time is extended
Solution Approach 1:
The patent merges multiple individual contact hole etching operations into a single line-shaped etching process. The line-shaped mask opening allows etchant to reach multiple contact holes simultaneously through the line structure, combining what would otherwise be separate, time-consuming etching steps into one efficient operation while maintaining precise alignment
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces the distance between contact plugs and gate electrodes, shortening the length of sense amplifiers and enabling downscaling of DRAM and other circuits, thereby reducing chip area and improving manufacturing efficiency.
Implementation Method 1
the silicon oxide film is selectively etched by using a mask, thereby providing holes on the source/drain regions
Data Source
AI summary
To provide a manufacturing method of a semiconductor memory device, the method including forming contact plugs to be connected to a drain region or a source region of each of transistors, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having a line-shaped opening provided across the contact plugs. Each of the transistors constituting a sense amplifier that amplifies a potential difference between bit lines is a ring-gate transistor.