Line-Shaped Interposer Vias for Thermal and Power Integrity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional RDL structures with circular or square-shaped openings in dielectric layers limit via size, resulting in convex surfaces and restricted polymer area, leading to inadequate power integrity and thermal performance in integrated circuits.
Innovation Solution
The introduction of line-shaped vias in enhanced shape openings, such as strip, L, U, H, circular ring, or rectangular ring shapes, within dielectric layers to increase contact surface area between metal traces, providing a flat top surface and improved thermal and power integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If circular or square-shaped openings are used in dielectric layers, then the via structure is simple to manufacture, but the contact surface area between metal traces is limited, resulting in inadequate power integrity and thermal performance
Solution Approach 1:
The patent applies asymmetry by transitioning from symmetric circular or square via shapes to asymmetric line-shaped via structures. This asymmetric line shape extends in one primary direction, maximizing the contact surface area between metal traces while maintaining manufacturability through standard photolithography and etching processes that can accommodate elongated geometries.
Solution Approach 2:
The invention utilizes dimensionality change by extending the via structure from a compact 2D circular/square footprint to a linear 1D-dominated shape that spans across multiple dielectric layers. This line-shaped configuration increases the effective contact surface area by distributing the connection across a longer path while maintaining a narrow width, thereby improving power integrity and thermal performance without significantly increasing manufacturing complexity.
2Reliability
If conventional circular or square via shapes are used, then the manufacturing process is straightforward, but the polymer area is restricted and convex surfaces are formed, limiting thermal and power performance
Solution Approach 1:
The patent applies asymmetry by transitioning from symmetric circular or square via shapes to asymmetric line-shaped via structures. This asymmetric line shape extends in one primary direction, maximizing the contact surface area between metal traces while maintaining manufacturability through standard photolithography and etching processes that can accommodate elongated geometries.
Solution Approach 2:
The invention applies local quality by concentrating the via structure's contact area along a specific linear path where it is most needed for power integrity and thermal performance. The line-shaped via provides enhanced local connection quality between metal traces at critical interfaces, while the surrounding dielectric material maintains its insulating properties, creating optimized local electrical and thermal characteristics.
3Reliability
If larger via sizes are used to increase contact surface area, then power integrity and thermal performance improve, but convex surfaces are formed and polymer area is restricted
Solution Approach 1:
The invention utilizes dimensionality change by extending the via structure from a compact 2D circular/square footprint to a linear 1D-dominated shape that spans across multiple dielectric layers. This line-shaped configuration increases the effective contact surface area by distributing the connection across a longer path while maintaining a narrow width, thereby improving power integrity and thermal performance without significantly increasing manufacturing complexity.
Solution Approach 2:
The invention applies local quality by concentrating the via structure's contact area along a specific linear path where it is most needed for power integrity and thermal performance. The line-shaped via provides enhanced local connection quality between metal traces at critical interfaces, while the surrounding dielectric material maintains its insulating properties, creating optimized local electrical and thermal characteristics.
Data Source
AI summary
An interposer may include a first metal trace located on a first dielectric layer, a second dielectric layer located on the first dielectric layer, a line-shaped via located in the second dielectric layer and connected to the first metal trace, and a second metal trace located on the second dielectric layer and connected to the line-shaped via.


