Linear Address Remapping Logic for Memory Power Optimization
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Solution Overview
Problem
Current memory systems that employ interleaving to improve performance consume relatively more power, and there is a need for a more efficient power usage method, especially in situations where accessing a single DRAM is sufficient without adverse effects on system performance.
Innovation Solution
A system-on-chip with linear address remapping logic that selectively remaps addresses from a modem processor to allow for either interleaving or linear access operations between multiple memory devices, optimizing power usage by partitioning addresses into interleaving and linear access areas and adjusting the most significant bit to determine access methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If interleaving access operation is used on multiple memory devices, then system performance is improved, but power consumption increases
Solution Approach 1:
The system dynamically switches between interleaving access mode and linear access mode based on operational requirements. The memory controller can selectively enable interleaving for performance-critical operations while using linear access for power-saving scenarios, making the memory access pattern adaptive rather than static.
Solution Approach 2:
The invention changes the address mapping parameters through linear address remapping logic. By remapping addresses to identify which memory devices should be accessed and in what pattern, the system can transform standard linear addresses into interleaved addresses or keep them linear, thereby controlling the access mode through parameter transformation.
2Productivity
If interleaving access operation is used on multiple memory devices, then data throughput is improved, but device complexity increases
Solution Approach 1:
The linear address remapping logic acts as an intermediary component between the processor and the memory controller. It translates processor-generated linear addresses into appropriate addresses for the memory subsystem, handling the complexity of interleaving decisions without burdening the processor or the memory devices themselves.
3Use of energy by moving object
If linear access operation is used on a single memory device, then power consumption is reduced, but system performance may be adversely affected
Solution Approach 1:
The system applies interleaving access partially rather than universally. The linear address remapping logic identifies specific address ranges or patterns that would benefit from interleaving and applies it only to those cases, while using linear access for other operations where performance impact would be minimal, thus achieving partial optimization.
Data Source
AI summary
A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address.