Linear Address Tag Table for Hardware Memory Isolation

Solution Overview

Problem

Current computer processors lack effective memory isolation between software components within the same process address space, leading to security vulnerabilities where a bug in one component can compromise the entire application, and existing solutions like process isolation result in performance and memory overhead.

Innovation Solution

The introduction of a linear address tag table (LATT) that extends page table lookups with additional metadata, allowing hardware-enforced memory isolation by associating memory access tags with sandbox IDs and ensuring that only matching tags allow memory access, thereby preventing unauthorized access between components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If process isolation is used to provide memory isolation between components, then security is improved, but memory overhead and performance latency increase

Engineering Contradiction:

Improvememory isolation securityVSAvoidperformance latency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent divides the address space into multiple compartments using compartment identifiers (CIDs) that are embedded in address tags. Each component is assigned a specific compartment, creating logical segmentation without requiring separate process address spaces. This allows memory isolation between components while keeping them in the same process, avoiding the overhead of process isolation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces address tags as an intermediary mechanism between the virtual address and physical address translation process. These tags carry compartment identification information that enables memory isolation checks during address translation, providing security without requiring full process isolation overhead.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If process isolation is used to provide memory isolation between components, then security is improved, but memory overhead increases

Engineering Contradiction:

Improvememory isolation securityVSAvoidmemory overhead

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The patent divides the address space into multiple compartments using compartment identifiers (CIDs) that are embedded in address tags. Each component is assigned a specific compartment, creating logical segmentation without requiring separate process address spaces. This allows memory isolation between components while keeping them in the same process, avoiding the overhead of process isolation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent merges multiple components into a single process address space while maintaining isolation through compartment tags. By combining components that would traditionally require separate processes into one address space with tag-based compartmentalization, the system reduces memory overhead while preserving security boundaries.

Inventive Principle:

Principle #5Merging (Combining)

3Device complexity

If traditional page tables are used without additional metadata, then address translation is simple, but memory isolation between components is not enforced

Engineering Contradiction:

Improveaddress translation complexityVSAvoidmemory isolation enforcement

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent introduces address tags as an intermediary mechanism between the virtual address and physical address translation process. These tags carry compartment identification information that enables memory isolation checks during address translation, providing security without requiring full process isolation overhead.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent adds a new dimension to address translation by incorporating compartment identifiers into the address tag structure. This additional dimension enables memory isolation enforcement without fundamentally changing the core page table translation mechanism, maintaining relative simplicity while adding security capabilities.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11741018B2Apparatus and method for efficient process-based compartmentalization

Publication Date: 2023.08.29 INTEL CORP

AI summary

An apparatus and method for efficient process-based compartmentalization. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data; memory management circuitry coupled to the execution circuitry, the memory management circuitry to manage access to a system memory by a plurality of related processes using one or more process-specific translation structures and one or more shared translation structures to be shared by the related processes; and one or more control registers to store a process-specific base address pointer associated with a first process of the plurality of related processes and to store a shared base address pointer to identify the shared translation structures; wherein the memory management circuitry is to use the process-specific base address pointer in combination with a first linear address provided by the first process to walk the process-specific translation structures to identify any permissions and/or physical address associated with the first linear address, wherein if permissions are identified, the memory management circuitry is to use the permissions in place of any permissions specified in the shared translation structures.