Linear Array Display for Logic Design State Encoding

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Solution Overview

Problem

Complexity in logic element relationships in logic designs leads to undefined, unexamined, and un-simulated interactions, causing unexpected behaviors and potential malfunctions in systems, especially in critical systems.

Innovation Solution

Encoding logic designs as linear arrays that include binary output and input variables, minterms, maxterms, present and next state values, and displaying them as combination maps to identify and correct undefined relationships, thereby simplifying manipulation and enhancing robustness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If logic designs incorporate numerous logic elements and logic element relationships, then functionality and complexity of the logic design increases, but many logic element relationships become undefined and unexamined

Engineering Contradiction:
Improvefunctionality of logic designVSAvoiddefinedness of logic element relationships
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent segments the logic design into a linear array of logic states, where each state is explicitly defined with present state values, next state values, minterms, and maxterms. This segmentation transforms the complex, potentially undefined relationships into discrete, examinated units, allowing systematic identification and resolution of undefined relationships while maintaining overall functionality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary encoding of the logic design into a linear array format before analysis. By pre-organizing the logic elements into structured states with explicit definitions, the system enables subsequent examination and identification of undefined relationships without requiring reanalysis of the entire design, thus improving reliability while preserving functionality.

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If logic element relationships are not examined and simulated, then design complexity is reduced, but unexpected behaviors and malfunctions occur

Engineering Contradiction:
Improvecomplexity of logic designVSAvoidunexpected behaviors and malfunctions
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent implements a feedback mechanism where the linear array representation enables systematic examination of logic element relationships. By displaying the encoded logic design as a linear array with explicit state transitions, the system identifies undefined relationships and allows for correction, thereby eliminating unexpected behaviors while maintaining manageable complexity through the structured representation.

Inventive Principle:
Principle #23Feedback

3Ease of operation

If logic designs are encoded as linear arrays with multiple fields, then manipulation and analysis become easier, but the representation becomes more complex

Engineering Contradiction:
Improveease of manipulation and analysisVSAvoidcomplexity of linear array representation
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent transforms the logic design representation by changing the organizational parameters from traditional multidimensional logic representations to a linear array format. Each logic state is encoded with specific parameters (present state values, next state values, minterms, maxterms), which simplifies manipulation and analysis operations while the linear structure manages the representational complexity through systematic organization.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9396298B1Linear array display
Publication Date: 2016.07.19 ASSURANT DESIGN AUTOMATION LLC
  • US9396298B1 patent drawing
  • US9396298B1 patent drawing
  • US9396298B1 patent drawing

AI summary

For linear array display, a method encodes a logic design as a linear array that includes a plurality of logic states. Each logic state includes one or more binary output variables, one or more binary input variables, one or more minterms of the one or more binary input variables, one or more maxterms of the one or more minterms, one or more present state values, and one or more next state values. The method displays the linear array as a combination map comprising a plurality of fields. Each field represents a corresponding logic state.