Linear Combiner Sub-Weight Decomposition for Low-Power ADC Correction
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Solution Overview
Problem
Existing RF sampling receivers face challenges in achieving low power consumption due to the large number of taps and complex mathematical functions required in linear combiners, which are necessary to correct gain and phase mismatches between interleaved analog-to-digital converters (ADCs).
Innovation Solution
The implementation of a linear combiner with a plurality of operator circuits that apply weighting factors using a sub-weight decomposition method, dividing taps into high, medium, and low tiles, and using dithered quantization to reduce the number of multipliers and minimize power consumption while maintaining correction accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large number of taps and complex mathematical functions are used in the linear combiner to correct gain and phase mismatches, then the correction accuracy is improved, but the power consumption and device complexity increase
Solution Approach 1:
The patent segments the weighting factors into multiple sub-weighting factors (e.g., integer part, fractional part, sign bit) and processes them separately through different operator circuits. This segmentation allows each operator to handle simpler computations with reduced complexity while maintaining overall correction accuracy through the combination of processed sub-weights.
Solution Approach 2:
The patent transforms the single-dimension complex multiplication operation into a multi-dimension processing approach by decomposing weighting factors into multiple sub-components (integer, fractional, sign bits) and processing them through separate operator circuits operating in parallel, effectively adding a dimensional aspect to the computation process.
2Measurement precision
If a large number of taps and complex mathematical functions are used in the linear combiner to correct gain and phase mismatches, then the correction accuracy is improved, but the power consumption increases
Solution Approach 1:
The patent segments the weighting factors into multiple sub-weighting factors (e.g., integer part, fractional part, sign bit) and processes them separately through different operator circuits. This segmentation allows each operator to handle simpler computations with reduced power consumption while maintaining overall correction accuracy through the combination of processed sub-weights.
Solution Approach 2:
The patent applies partial action by using dithered quantization that introduces controlled noise to reduce the precision requirements of individual operator circuits. This allows each operator to perform simpler, lower-power computations while the cumulative effect of multiple operators maintains the required overall accuracy.
3Use of energy by moving object
If the number of operator circuits is reduced to lower power consumption, then the power usage is improved, but the ability to maintain correction accuracy deteriorates
Solution Approach 1:
The patent segments the weighting factors into multiple sub-weighting factors that can be processed by fewer, simpler operator circuits. Each segment is processed with reduced precision requirements through dithered quantization, allowing the use of fewer operators while maintaining overall accuracy through the combination of all processed segments.
Solution Approach 2:
The patent introduces dithered quantization as an intermediary process between the input signal and the operator circuits. This intermediary adds controlled noise that masks quantization errors, allowing the use of fewer and simpler operators while maintaining the required output accuracy.
4Measurement precision
If traditional linear combiner methods are used, then the correction quality is maintained, but the complexity and power consumption are high
Solution Approach 1:
The patent segments the weighting factors into multiple sub-weighting factors (e.g., integer part, fractional part, sign bit) and processes them separately through different operator circuits. This segmentation allows each operator to handle simpler computations with reduced complexity while maintaining overall correction accuracy through the combination of processed sub-weights.
Solution Approach 2:
The patent transforms the single-dimension complex multiplication operation into a multi-dimension processing approach by decomposing weighting factors into multiple sub-components (integer, fractional, sign bits) and processing them through separate operator circuits operating in parallel, effectively adding a dimensional aspect to the computation process.
Data Source
AI summary
In accordance with an example, an integrated circuit includes a linear combiner having an input for receiving a signal. The linear combiner also has a plurality of operator circuits for applying weighting factors to the signal, in which a first operator circuit in the plurality of operator circuits performs a first operation on the signal using a first sub-weight of one of the weighting factors to provide a first tile output and a second operator circuit in the plurality of operator circuits performs a second operation on the signal using a second sub-weight of the one of the weighting factors to provide a second tile output. The linear combiner also has an adder having a first input coupled to receive the first tile output and the second tile outputs and providing a combined output.