Linear Doherty Power Amplifier for Linearity and Back-Off Efficiency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current power amplifiers face a trade-off between average-power efficiency and inherent linearity, particularly in modern wireless communication systems with high peak-to-average power ratio signals, where existing linearization techniques are either inefficient or impractical for 5G digital MIMO systems.
Innovation Solution
A Doherty power amplifier arrangement with multiple main amplifier circuits in parallel and at least one auxiliary amplifier circuit, where transistors of different sizes and bias voltages are used to optimize linearity through derivative superposition, and Doherty load modulation is employed to extend linearity from back-off to peak power levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional power amplifiers are used to amplify RF signals, then output power is increased, but distortion signals are generated due to intrinsic nonlinearity
Solution Approach 1:
The power amplifier is divided into multiple transistor cells connected in parallel, each with different sizes and bias conditions. This segmentation allows each cell to contribute differently to the overall output, with larger cells handling fundamental power amplification and smaller cells compensating for distortion components through their non-linear characteristics.
Solution Approach 2:
Different transistor cells are biased at different operating points and have different size characteristics tailored to their specific roles. The larger transistors are optimized for high-power operation while smaller transistors are optimized for linearity and distortion compensation, creating local quality variations that collectively improve overall performance.
2Power
If power amplifiers are operated at high output power levels, then signal transmission capability is improved, but average-power efficiency deteriorates at back-off power levels
Solution Approach 1:
The bias conditions of the transistor cells are dynamically adjusted based on the operating power level. At peak power levels, all cells operate at optimal efficiency points, while at back-off power levels, the biasing scheme automatically reconfigures to maintain higher efficiency by reducing quiescent current consumption in less active cells.
Solution Approach 2:
The operating parameters (bias voltages and currents) of the transistor cells are changed according to the signal power level. This allows the amplifier to adapt its efficiency characteristics dynamically, maintaining high average-power efficiency across varying operating conditions while preserving peak power capability.
3Object-generated harmful factors
If multiple transistor cells with different sizes and biases are used to improve linearity, then inherent linearity is improved, but device complexity increases
Solution Approach 1:
The transistor cells are designed with asymmetric characteristics - different sizes, different bias points, and different positioning in the parallel configuration. This asymmetric design allows a small number of cells to effectively cancel distortion components through their complementary non-linearities, achieving linearity improvement without requiring a large number of identical cells.
Data Source
Figure 1a
Figure 1b
Figure 2
AI summary
An amplifier arrangement (100) comprises a power splitter (110) configured to receive the input signal and produce split input signals (101, 102,...,10N, 113). The amplifier arrangement (100, 200) further comprises a first amplifier branch (120) comprising multiple main amplifier circuits (121, 122,...,12N). Output signals of the multiple main amplifier circuits are combined to generate a first output signal (150). The amplifier arrangement (100, 200) further comprises a second amplifier branch (130) comprising at least one auxiliary amplifier circuit (131). The at least one auxiliary amplifier circuit (131) is configured to receive a split input signal from the power splitter (110) and produce a second output signal (160). The amplifier arrangement (100) further comprises a power combiner (170) configured to receive the first (150) and second (160) output signals and produce the output signal for delivering to the load (180).