Linear Duty Cycle Correction Circuit for Memory Clock Distortion
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Solution Overview
Problem
Existing duty cycle correction circuits in memory interfaces lack linearity, leading to distorted clock signals that hinder timing closure at higher speeds due to duty cycle distortion introduced by the clock network inside memory.
Innovation Solution
A programmable linear duty cycle correction circuit with a series-connected charging and discharging circuit, utilizing transistors or resistors, is implemented to pre-emptively correct the duty cycle of the clock signal, ensuring linear correction across different duty cycle correction codes and minimizing silicon area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional duty cycle correction circuits are used, then duty cycle distortion is corrected, but linearity is poor causing timing closure issues at higher speeds
Solution Approach 1:
The duty cycle correction circuit is segmented into multiple independent leg circuits (first leg circuit, second leg circuit, etc.), each handling a specific portion of the correction range. This segmentation allows each leg to be optimized for its specific duty cycle range, improving overall linearity and timing closure at higher speeds.
Solution Approach 2:
Each leg circuit is designed with specific transistor configurations and sizing tailored to its intended operating range. The first leg circuit uses different transistor arrangements compared to the second leg circuit, allowing each to provide optimal correction characteristics for its specific duty cycle range, thereby improving linearity across the full operating range.
2Adaptability or versatility
If more transistors are added to improve correction range, then duty cycle correction capability increases, but silicon area increases
Solution Approach 1:
The circuit employs programmable transistor configurations where the number of transistors in each leg can be dynamically adjusted based on the required correction amount. This allows the circuit to adapt to different duty cycle correction needs without permanently occupying maximum silicon area, achieving versatility with area efficiency.
Solution Approach 2:
The leg circuits are designed with nested transistor structures where transistors are arranged in series and parallel configurations that share common nodes and control signals. This nesting allows multiple correction functions to be implemented within a compact area, reducing overall silicon footprint while maintaining correction range.
Data Source
AI summary
Examples describe a duty cycle correction circuit for correcting duty cycle distortion from memory. One example is an integrated circuit for correcting an input clock signal. The integrated circuit includes a first leg circuit and a second leg circuit. The first leg circuit and the second leg circuit both comprise a charging circuit and a discharging circuit. Each charging circuit comprises a first plurality of transistors and each discharging circuit comprises a second plurality of transistors. The charging circuit is coupled to the discharging circuit in series. A number of transistors of the first plurality of transistors in the first leg circuit is different from a number of transistors of the first plurality of transistors in the second leg circuit.