Linear Equalizer Peaking Gain Control at Low Supply Voltage
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Solution Overview
Problem
Traditional linear equalizers with programmable peaking gain and stacked or cascode transistors have high power consumption due to higher supply voltage, making them unsuitable for applications with limited budgets.
Innovation Solution
A linear equalizer design that includes sets of transistors, a resistor, and impedance elements connected between input and output terminals, with programmable peaking gain achieved by adjusting the DC component of the input signal applied to the transistors, allowing for reduced power consumption by eliminating stacked transistors and using BJTs or FETs with impedance elements like resistors, inductors, and capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If stacked or cascode transistors are used to achieve programmable peaking gain, then the peaking gain control is effective, but the power consumption increases due to higher supply voltage
Solution Approach 1:
The patent changes the operating parameters of the transistors by adjusting the DC component of the input signal, which modifies the transconductance of the transistors to achieve programmable peaking gain without requiring higher supply voltage or stacked transistor configurations
Solution Approach 2:
The patent implements dynamic control of the peaking gain by allowing the DC component of the input signal to vary the transistor characteristics in real-time, enabling programmable gain adjustment while maintaining low supply voltage operation
2Adaptability or versatility
If stacked or cascode transistors are used for programmable peaking gain, then the peaking gain is controllable, but the supply voltage requirement increases
Solution Approach 1:
The patent achieves programmable peaking gain by changing the DC bias conditions and transconductance parameters of the transistors through input signal adjustment, eliminating the need for stacked or cascode configurations that require higher supply voltage
3Adaptability or versatility
If traditional linear equalizer architecture with stacked transistors is used, then programmable peaking gain is achieved, but the device complexity and power budget requirements increase
Solution Approach 1:
The patent simplifies the device architecture by using basic transistor configurations with adjustable DC bias conditions, achieving programmable peaking gain through parameter modulation rather than complex stacked or cascode transistor structures
Solution Approach 2:
Instead of using complex transistor stacking to achieve gain control, the patent inverts the approach by using simple transistor configurations controlled by DC component adjustment of the input signal, thereby achieving the same functionality with reduced complexity
Data Source
AI summary
Embodiments of linear equalizers are disclosed. In an embodiment, a linear equalizer includes sets of transistors, a resistor, and first and second impedance elements. The sets of transistors are connected between at least one input terminal of the linear equalizer and at least one output terminal of the linear equalizer. The resistor is connected to a supply voltage, to the at least one output terminal, and to the sets of transistors. The first and second impedance elements are connected between emitter terminals or source terminals of the sets of transistors and at least one fixed voltage. A peaking gain of the linear equalizer is programmable by adjusting a direct current (DC) component of at least one input signal that is received at the at least one input terminal and that is applied to the sets of transistors.