Linear Gate Structure for OTP Memory Voltage Control
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Solution Overview
Problem
Precise control of programming voltage in anti-fuse type one-time-programmable (OTP) memory devices is challenging, especially when scaling down, due to susceptibility to lithography and etching inaccuracies in the manufacturing process.
Innovation Solution
The method involves forming an active region with a linear top view shape and a gate structure with a linear portion intersecting a section of the active region away from its end portions, surrounded by insulating layers, to improve control over the gate coupling area and threshold voltage, thereby reducing the impact of manufacturing inaccuracies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the anti-fuse type OTP memory device is scaled down, then the device size is reduced, but the control precision of programming voltage deteriorates due to lithography and etching inaccuracies
Solution Approach 1:
The active region is segmented into multiple sections along its length, with the gate structure positioned to overlap only a middle section away from end portions. This segmentation isolates the critical gate coupling area from regions susceptible to lithography and etching inaccuracies at the ends, thereby maintaining manufacturing precision while enabling device scaling.
Solution Approach 2:
The gate structure is positioned to overlap with a specific middle section of the active region, creating a localized gate coupling area with controlled properties. This local quality approach ensures that the critical programming voltage control is concentrated in a region less affected by manufacturing variations, while other regions can be optimized for different functions.
2Area of stationary object
If the gate structure overlaps with end portions of the active region, then the gate coupling area is increased, but the threshold voltage control is worsened due to manufacturing inaccuracies
Solution Approach 1:
The active region is divided into a middle section (overlapped by gate) and end portions (not overlapped). This segmentation allows the gate coupling area to be sufficiently large for proper transistor operation while excluding the end portions that are most susceptible to lithography and etching inaccuracies, thereby maintaining threshold voltage control.
Solution Approach 2:
The gate structure is deliberately positioned to overlap with a middle section of the active region during the design and fabrication process, before manufacturing variations occur. This preliminary positioning ensures that the critical gate coupling area is established in a region that will be less affected by subsequent manufacturing inaccuracies.
Data Source
AI summary
The present application provides a method for preparing a memory device. The method includes: forming an active region in a substrate, wherein the active region has a linear top view shape; forming a gate structure on the substrate, wherein the gate structure has a linear portion intersected with a section of the active region away from end portions of the active region; forming a first insulating layer and a second insulating layer on the substrate, wherein the first insulating layer laterally surrounds the gate structure, and is covered by the second insulating layer; forming an opening penetrating through the first and second insulating layers and exposing a portion of the active region, wherein the opening is laterally spaced apart from the gate structure; and sequentially forming a dielectric layer and an electrode in the opening.