Linear Transconductance Amplifier Using Source Degeneration
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Solution Overview
Problem
Conventional transconductance amplifiers face challenges in achieving high linearity due to large parasitic capacitance, which limits their speed when using NMOS transistors with long channel lengths.
Innovation Solution
The implementation of a circuit comprising common-source amplifiers, diode-connected devices, and a source-degenerating resistor to maintain high linearity without the need for long channel lengths, utilizing NMOS transistors and PMOS transistors in diode-connected topologies to manage impedance and provide source degeneration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If NMOS transistors with long channel lengths are used to improve linearity, then linearity is improved, but parasitic capacitance increases and speed is limited
Solution Approach 1:
The patent changes the circuit topology parameters by introducing source-degenerating resistors and diode-connected devices, allowing the use of short-channel transistors while maintaining linearity. This transforms the approach from relying on physical dimension changes (channel length) to circuit configuration changes, thereby improving speed without sacrificing linearity.
Solution Approach 2:
Source-degenerating resistors are introduced as intermediary elements between the transistor sources and ground. These resistors provide negative feedback that linearizes the transistor operation, enabling high linearity with short-channel devices. The diode-connected devices serve as additional intermediaries to control the source voltages and maintain proper biasing conditions.
2Measurement precision
If NMOS transistors with long channel lengths are used to improve linearity, then linearity is improved, but parasitic capacitance increases
Solution Approach 1:
The patent changes the circuit configuration by adding source-degenerating resistors and diode-connected devices, which compensates for the reduced linearity inherent in short-channel transistors. This allows the use of transistors with smaller physical dimensions, thereby reducing parasitic capacitance while maintaining acceptable linearity through circuit-level correction.
Solution Approach 2:
The patent converts the typically harmful non-linear behavior of short-channel transistors into a manageable characteristic by using source-degenerating resistors to provide linearizing negative feedback. This approach turns the potential disadvantage of short-channel devices into an opportunity to reduce parasitic capacitance while maintaining linearity through active compensation.
3Measurement precision
If source-degenerating resistor is introduced to maintain linearity, then linearity is maintained, but device complexity increases
Solution Approach 1:
The diode-connected devices serve multiple functions: they provide biasing for the source-degenerating resistors, establish proper operating points for the transistors, and contribute to the overall linearization mechanism. This multi-functionality reduces the need for additional dedicated components, thereby limiting the increase in device complexity.
Solution Approach 2:
The patent merges the biasing function and the linearization function into a unified circuit structure where diode-connected devices and source-degenerating resistors work together. This integration avoids the need for separate biasing circuits and linearization networks, thereby minimizing the increase in device complexity while achieving the desired linearity.
Data Source
AI summary
A circuit includes a first common-source amplifier configured to receive a first voltage at a first gate node and output a first current to a first drain node in accordance with a first source voltage at a first source node; a second common-source amplifier configured to receive a second voltage at a second gate node and output a second current to a second drain node in accordance with a second source voltage at a second source node; a first diode-connected device configured to couple the first source node to a DC (direct current) node; a second diode-connected device configured to couple the second source node to the DC node; and a source-degenerating resistor inserted between the first source node and the second source node.