Linear Memory Management Unit for 16-bit Microcontroller Address Extension
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Solution Overview
Problem
8/16-bit microcontrollers are limited in accessing memory above 64 Kbytes due to their 16-bit program counter and inefficient paging access mechanisms, which result in non-linear and non-contiguous memory access, leading to performance issues when dealing with large memory spaces.
Innovation Solution
A linear memory management unit (LMMU) with an extended addressable 'L' register that exceeds the program counter limits, enabling contiguous data access through an auto-incrementing pointer, supporting byte and multi-byte access, and eliminating the need for page boundary checks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If paging access mechanisms are used to access physical memory, then the addressable memory range can be extended beyond 64K, but the memory access becomes non-linear and non-contiguous, severely impacting performance
Solution Approach 1:
The memory system is segmented into pages that can be independently managed. The LMMU divides the extended address space into manageable page segments, allowing the processor to access only the necessary pages rather than the entire address space, thus maintaining performance while extending addressability.
Solution Approach 2:
The LMMU acts as an intermediary between the 16-bit processor and the extended physical memory. It translates 16-bit addresses into extended physical addresses, enabling the processor to access memory beyond 64K without requiring the processor itself to be modified, thereby maintaining compatibility while extending capability.
2Area of stationary object
If code is executing from paged memory, then data access requires calling routines in unpaged memory, but this increases device complexity and reduces ease of operation
Solution Approach 1:
The LMMU provides self-service by automatically managing page translations and data access operations. When code executes from paged memory, the LMMU automatically handles the translation and data retrieval without requiring explicit calls to unpaged memory routines, thus simplifying operation while maintaining extended memory capacity.
3Quantity of substance
If data spans multiple pages, then significant effort is expended to check and update page boundaries, but this increases loss of time and reduces productivity
Solution Approach 1:
The LMMU performs preliminary actions by pre-loading and pre-translating page data before it is needed. When data spans multiple pages, the LMMU proactively manages the page boundaries and prepares the necessary data in advance, eliminating the need for runtime page boundary checks and updates, thus reducing time loss while maintaining large data storage capacity.
Data Source
AI summary
A memory management unit comprises register and control logic and arranged to support a microprocessor controller unit accessing physical address space via an address bus wherein the microprocessor controller unit comprises a program counter having a first address size, the memory management unit wherein the register and control logic comprises a register having a second address size greater than the first address size and arranged to provide an extended address bus between the microprocessor controller unit and physical address space.