Linear PFD Fractional PLL With Adjustable Delay Modulation
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Solution Overview
Problem
Existing fractional-N phase locked loops (PLLs) are complex and power-intensive due to the need for dual-mode dividers and sigma-delta modulators to achieve non-integer frequency ratios, limiting their resolution and efficiency.
Innovation Solution
A fractional PLL with a linear phase frequency detector and an adjustable delay block, which modulates the output frequency by varying the transition times of the up and down signals, eliminating the need for dual-mode dividers and sigma-delta modulators, and using a current-mode logic stage or cascaded inverters for adjustable delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dual-mode dividers and sigma-delta modulators are used to achieve fractional-N PLL, then non-integer frequency ratios can be achieved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts and removes the sigma-delta modulator and dual-mode divider from the traditional fractional-N PLL architecture. Instead, it uses a linear phase frequency detector with an adjustable delay block to achieve fractional frequency ratios, thereby eliminating the complexity and power consumption associated with the removed components while maintaining the ability to generate non-integer frequency ratios.
Solution Approach 2:
The patent inverts the traditional approach by placing the adjustable delay in the phase frequency detector path rather than using a complex divider. This inversion allows the system to achieve fractional-N functionality through delay modulation instead of through complex division and modulation, significantly simplifying the overall architecture.
2Adaptability or versatility
If dual-mode dividers and sigma-delta modulators are used to achieve fractional-N PLL, then non-integer frequency ratios can be achieved, but power consumption increases
Solution Approach 1:
The patent extracts and removes the power-intensive sigma-delta modulator and dual-mode divider components. The remaining architecture uses a linear phase frequency detector with an adjustable delay block, which consumes significantly less power while still achieving the required fractional frequency ratios through delay-based modulation.
Solution Approach 2:
The patent replaces expensive, power-consuming components (sigma-delta modulator and dual-mode divider) with simpler, lower-power alternatives (adjustable delay block and linear PFD). This substitution achieves the same functional goal with much lower power overhead, making the system more energy-efficient.
3Device complexity
If integer-N PLL is used, then the design is simple, but the output frequency resolution is limited to N times the reference frequency resolution
Solution Approach 1:
The patent introduces dynamics into the phase frequency detector by adding an adjustable delay block that can be dynamically controlled. This dynamic element allows the system to achieve variable frequency ratios including fractional values, thereby improving output frequency resolution without significantly increasing overall design complexity compared to static integer-N PLLs.
Solution Approach 2:
The patent changes the delay parameter in the phase frequency detector to achieve different frequency ratios. By adjusting the delay block's delay value, the system can generate a range of output frequencies with fine resolution, overcoming the fixed resolution limitation of integer-N PLLs while maintaining design simplicity.
Data Source
AI summary
A phase-locked loop. The phase-locked loop includes a voltage-controlled oscillator having: a control input, and a clock output; and a phase frequency detector having: a reference clock input, a feedback clock input, an up output configured to be either in a set state or a reset state, and a down output configured to be either in a set state or a reset state. The up output and the down output are connected to the control input. The clock output is connected to the feedback clock input. The phase frequency detector includes an adjustable delay block configured to delay, by an adjustable delay time: a transition of the up output from the set state to the reset state, and a transition of the down output from the set state to the reset state.