Linear PLL Circuit for Fast Locking in Small Die Area
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Solution Overview
Problem
Analog phase-locked loops (PLLs) used in integrated circuits without a digital core face challenges in achieving small die area and short settling time, especially at low input frequencies, due to increased loop filter component sizes and longer settling times.
Innovation Solution
The implementation of a PLL circuit that includes a frequency divider, phase detector, and linear frequency-to-analog converters to generate control signals for a linear oscillator, allowing for efficient frequency and phase alignment of the PLL output with the input signal, while minimizing die area and settling time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If charge-pump based analog PLL is used to achieve smaller settling time, then settling time is reduced, but loop bandwidth must be widened which increases filter component sizes and die area
Solution Approach 1:
The patent changes the fundamental operating parameters of the PLL by using a digital architecture with a different frequency synthesis approach. Instead of using a charge pump with analog filtering, the invention employs a digital phase detector, a differentiator, and a frequency accumulator that operates with discrete time steps. This parameter change allows the system to achieve fast settling without requiring large analog filter components, thus reducing die area while maintaining short settling time.
Solution Approach 2:
The patent substitutes the mechanical/analog charge pump and analog filter system with a digital system consisting of a phase detector, differentiator, and frequency accumulator implemented in digital logic. This replacement eliminates the need for large physical filter components (capacitors and resistors) while achieving comparable or better settling performance through digital signal processing techniques.
2Adaptability or versatility
If analog PLL is designed for low input frequencies, then frequency tracking is achieved, but loop filter component sizes must be increased which lengthens settling time
Solution Approach 1:
The patent implements a dynamic digital filtering approach where the differentiator and frequency accumulator adapt to the input frequency characteristics. The digital system can dynamically adjust its response based on the frequency being tracked, allowing it to maintain accurate frequency tracking for low input frequencies without requiring fixed large-value analog filter components that would increase settling time.
Solution Approach 2:
The patent uses periodic sampling and digital accumulation techniques where the frequency accumulator integrates phase error information over discrete time periods. This periodic digital integration approach allows the system to achieve accurate low-frequency tracking through software-defined filtering rather than hardware filter components, thereby reducing settling time while maintaining tracking accuracy.
3Reliability
If loop filter component sizes are increased to meet stability requirements at low frequencies, then stability is improved, but die area grows considerably
Solution Approach 1:
The patent replaces the physical loop filter components (large capacitors and resistors) with a digital implementation using a differentiator and frequency accumulator. The stability function previously provided by analog filter components is now achieved through digital signal processing algorithms that compute the appropriate control signal without requiring large physical components, thus maintaining stability while dramatically reducing die area.
Solution Approach 2:
The patent changes the implementation domain from analog to digital, allowing stability to be achieved through software-defined parameters rather than fixed physical component values. The digital frequency accumulator can be configured with different accumulation rates and the differentiator can be tuned through digital parameters, providing stability without the area penalty of large analog filter components.
Data Source
AI summary
One example includes a phase-locked loop (PLL) circuit. The circuit includes a frequency divider and phase detector configured to generate a plurality of non-overlapping switching signals based on an input signal and a PLL output signal. The circuit also includes a linear frequency-to-current (F2I) converter configured to generate a control current having an amplitude that is based on the plurality of non-overlapping switching signals. The circuit further includes a linear current-controlled oscillator configured to generate the PLL output signal to have a frequency and phase to be approximately equal to the input signal based on the amplitude of the control current.