Linear Programming Clock Synchronization
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Solution Overview
Problem
Existing packet networks, such as those using Ethernet, lack inherent timing and synchronization capabilities, leading to issues like clock noise and interference in mobile backhaul networks, particularly affecting time-sensitive applications and causing dropped calls and delays in mobile communications.
Innovation Solution
A slave device connected to a master device over a network uses a linear programming approach to minimize clock offset and skew by formulating a problem that seeks to synchronize the slave clock with the master clock, using recorded timestamps and constraints to derive an accurate estimate of skew and offset, allowing for sub-microsecond level clock accuracy without assistance from the packet network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If packet-based clock recovery mechanism is used to synchronize slave clock with master clock, then timing information can be transmitted over packet networks, but packet delay variation and packet losses affect clock estimation accuracy and cause wander propagation to receiver clock signal
Solution Approach 1:
The patent introduces Boundary Clocks (BCs) and Transparent Clocks (TCs) as intermediary devices between master and slave clocks. These intermediaries actively compensate for packet delay variations and losses by measuring actual timing parameters and adjusting their timing information accordingly, thereby maintaining clock estimation accuracy without requiring direct end-to-end synchronization
Solution Approach 2:
The patent implements feedback mechanisms where Boundary Clocks and Transparent Clocks continuously monitor timing parameters (packet delay, jitter, losses) and adjust their timing information based on this feedback. This closed-loop approach allows the system to adapt to changing network conditions and maintain accurate clock synchronization despite packet delay variations and losses
2Adaptability or versatility
If adaptive timing technique is used at receiving terminal node to reconstruct timing signal, then synchronization can be achieved without network assistance, but presence of packet delay variation and packet losses causes transmitter clock to appear faster or slower than actual, propagating wander to receiver
Solution Approach 1:
Instead of relying on the receiving terminal node to independently reconstruct the timing signal through adaptive techniques, the patent introduces Boundary Clocks and Transparent Clocks as intermediary devices that actively manage timing information. These intermediaries measure actual packet delay and timing parameters, then provide corrected timing information to slave clocks, eliminating the need for complex adaptive reconstruction at the receiver and preventing wander propagation
3Reliability
If hop-by-hop Boundary Clocks or Transparent Clocks are used to assist timing transfer, then timing information can be distributed with network assistance, but device complexity increases compared to end-to-end synchronization
Solution Approach 1:
The patent segments the synchronization function by introducing optional intermediary devices (Boundary Clocks and Transparent Clocks) that can be deployed at specific network locations. Rather than requiring all network devices to perform complex timing functions, only specific nodes need to implement these intermediary mechanisms, while end devices can use simpler client/server synchronization modes
Data Source
AI summary
This invention relates to methods and devices for synchronization using linear programming, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a two-dimensional linear programming technique for estimating clock offset and skew, particularly from two-way exchange of timing messages between a master and a slave device. Some embodiments include a skew and offset adjustable free-running counter for regenerating the master time and frequency at the slave device.