Linear Programming for Multi-Patterning Layout Legalization
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Solution Overview
Problem
The complexity of modern integrated circuit design rules, particularly in analog, RF, and custom circuit designs, leads to laborious manual processes for checking and fixing design rule violations, especially with the introduction of multi-patterning technologies like double-patterning, which require efficient real-time detection and resolution of conflicts to maintain circuit density and manufacturability.
Innovation Solution
The approach models multi-patterning conflicts as linear difference constraints, allowing for a combined solution with design rule check constraints, using a Linear Program solver to iteratively check and fix feasibility, reducing the need for iterative Linear Program solver runs and enabling efficient resolution of conflicts by updating constraint graphs and estimating spacing shrinkage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If manual layout editing is used for analog, RF, and custom circuit designs, then design flexibility is maintained, but the process becomes laborious and time-consuming due to the large number of complex design rules
Solution Approach 1:
The patent replaces manual mechanical layout editing with an automated computer-based system that uses linear programming algorithms to detect and resolve multi-patterning conflicts and design rule violations automatically, eliminating the need for manual checking and fixing processes
Solution Approach 2:
The system enables self-service by automatically detecting multi-patterning conflicts and design rule violations, and autonomously resolving them through constraint-based optimization without requiring manual intervention from designers
2Measurement precision
If conventional DRC systems are used with powerful two-dimensional geometry engines, then design rule checking capability is enhanced, but computational complexity and processing time increase significantly
Solution Approach 1:
The patent replaces complex two-dimensional geometry engine operations with linear programming mathematical models that formulate design rule constraints as linear inequalities, enabling accurate checking through efficient linear algebra computations instead of complex geometric operations
Solution Approach 2:
The system changes the parameter representation from complex geometric operations to linear constraint parameters, transforming the problem into a linear programming formulation that can be solved efficiently using standard algorithms while maintaining checking accuracy
3Manufacturing precision
If multi-patterning technology is implemented to achieve finer feature spacing, then manufacturing precision is improved, but the number of constraints and computational effort for conflict detection increases
Solution Approach 1:
The patent merges multi-patterning conflict detection with design rule checking into a unified linear programming framework, where both types of constraints are formulated together and solved simultaneously, reducing overall computational complexity compared to separate processing approaches
Solution Approach 2:
The linear programming system serves multiple functions simultaneously: it detects multi-patterning conflicts, checks design rules, and optimizes layout configurations, making the system universally applicable to various constraint types without requiring separate specialized algorithms
4Reliability
If iterative Linear Program solver runs are performed to resolve multi-patterning conflicts, then solution accuracy is improved, but computational time and processing effort increase
Solution Approach 1:
The system performs preliminary action by formulating all multi-patterning and design rule constraints into a complete linear programming model before solving, allowing the solver to find the optimal solution in a single run without requiring multiple iterative executions, thus reducing computational time while maintaining accuracy
Data Source
AI summary
In a method for legalizing a multi-patterning integrated circuit layout including a plurality of islands, a set of multi-patterning constraints is generated on the basis of multi-patterning conflicts identified between the plurality of islands. Based on general design rule constraints and the multi-patterning constraints a combined set of layout constraints is generated. Feasibility of the set of layout constraints is checked, which then is provided to a Linear Program solver for generating an output circuit layout.


